Texas Instruments Corporation

Other

Matsushita Electric Industrial Co., Ltd.

Hiroshi Miyaguchi

Jim Childers

Naoya Tokunaga

Kenta Sokawa

Peter Reinecke

Yuji Yaguchi

Moo-Taek Chung

Tsuyoshi Akiyama

Jimmie D Childers

Yoichiro Miki

Masahiro Tani

Kazuki Ninomiya

Kazuhiro Ohara

Kenya Adachi

Manfred Becker

Gerard Chauvel

Takao Kojima

Hidetoshi Onuma

Tomohiko Kanemitsu

An ultrasound device generates polar-coordinate image data divided up into an (N&#xd7;M) array of polar-coordinate image data blocks; a first external memory configured to store the (N&#xd7;M) array of data blocks; a second external memory configured to store x-y coordinate image data corresponding to the polar-coordinate image data; a video processing chip comprising an internal memory configured to store an (N&#xd7;R) array of the polar-coordinate image data blocks; and a controller configured to perform a data conversion operation on the (N&#xd7;R) array of data blocks to generate x-y coordinate image data, and to store the x-y coordinate image data to the second external memory. N, M, and R are integers greater than 1; R is less than M; and an internal access time for the internal memory element is shorter than an external access time for the first external memory element.

System and method for converting scan data

The objective of the invention is to provide an image processing device that can operate at high speed even if input/output with respect to the outside is performed at low speed, and that can fully exploit processibility, by means of input line memoryand output line memorywhich can store image data of one scan line, and are arranged in the input unit and output unit, respectively; the input image data are written in input line memoryat the speed of the input image data; the image data that have been written to the input line memory are read at a speed n times faster than the input image data and are sent to processing unitor memory unitprocessing unitand memory unitreceive the image data of one scan line at a speed n times faster than the speed of the input image data, perform a prescribed processing, and then output the processing results at a speed n times faster than the speed of the input image data; the image data output from processing unitor memory unitare selected by selectorand written to output line memoryat a speed n times faster than the speed of the input image data; the output image data are read in units of one scan line from output line memoryat a prescribed speed.

Image processing device with a processing unit that processes image data in units of one scan line

The objective of the invention is to improve the processing efficiency of a system that repeatedly executes one instruction over multiple clock cycles. The SVP core of this SVP (Scan-line Video Processor) is made up of a three layer construction of the data input register (DIR) the SIMD type digital signal processing unit and the data output register (DOR) The SIMD type digital signal processing unit comprises a parallel arranged (connected) number of processing elements (PE to PEN&minus;1) (for example, 864 units) equal to the number of pixels N on one horizontal scan line. The instruction generator (IG) because the SVP core operates as an SIMD parallel processor, internally houses a RAM or ROM program memory that holds the desired program. The program stored in program memory contains not only the instructions (SIMD instruction) for the processing elements (PE to PEN&minus;1) of the processing unit but also such instructions (IG instruction) as jump, subroutine call, hardware interrupt, and the like. In this SVP when an IG instruction is read from the program memory while the repetitive processing of an SIMD instruction is being conducted in the SVP core the pertinent IG instruction is executed in parallel with the repetitive processing of the pertinent SIMD instruction.

Processor

A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Memory interface device and memory address generation device

A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including 8 plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Decrypting device

The television receiver including a display device capable of displaying a video signal having a predetermined display former of this invention includes; a plurality of video signal sources; a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.

Television receiver, video signal processing device, image processing device and image processing method

A method for loading of program data with high speed and efficiency along with eliminating the need for software modification even if changes occur in the storage addresses and data length of the program data stored in the program memory. In order to load program data in a rewritable manner into a number of functional circuits FC0, FC1, . . . , FCn operating in accordance with the supplied program data, a program memory, for example, a ROM 10, a program loader 12, and program designating apparatus, for example, a microprocessor 14, are provided in the system. In the ROM 10, multiple address pointers are stored in specified storage areas, and corresponding sets of program data are stored in the storage locations indicated by the address pointers in such a manner that a first set of program data is stored in the specified storage area which utilizes the address corresponding to the first address pointer as the start storage address, and a second set of program data is stored in the specified storage area which utilizes the address corresponding to the second address pointer as the start storage address.

Program loading method and apparatus

A single-instruction multiple-data (SIMD) processor (10) that incorporates features for horizontal scaling of video data. The processor (10) has a data input register (11) that is operable to store input data word in sequential locations in the data input register (11) and transfer the input data words to an array of processing elements. The processor (10) also has an output data register (16) operable to receive data output words from the array of processing elements and to output said data output words from sequential locations of said output data array. An input skip signal input to the processor causes a sequential data write operation to skip a location of the input data register while an output skip signal to the processor causes a sequential data read operation to skip a location of the output data register.

Single-instruction multiple-data processor with input and output

A timing and control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This circuit includes a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit.

Timing and control circuit and method for a synchronous vector processor

A synchronous vector processor (SVP) device (102) has a plurality of processing elements (150) which are comprised of an RF1 register (166), an ALU (164) and an RF0 (158). The processing elements are operable to be disposed between the data input register DIR (154) and the data output register (DOR) (168) to process data therebetween. Data is received in DIR (154), transferred to the processing elements (150), processed and then output to the DOR (168). A fast response clock operates the DIR (154) such that the jitter on the input signal is tracked. The Read clock on the DOR (168) is a stable clock. Data transferred between the DIR (154) and the DOR (168) is buffered in an elastic buffer to provide a time based compensation (TBC). To facilitate this, a buffer is implemented in either the RF1 (168) or the RF0 (158). A dual global rotation pointer is provided to generate two pointers that are asynchronous. The first pointer allows data to be transferred to the buffered area from/to the ALU (164) and the second pointer allows data to be transferred to the DOR (168) from the RF0 (158) or from a DIR (154) to the RF1 (166). A hardware interrupt is provided to perform this asynchronous transfer.

Apparatus and method for synchronizing data transfers in a single

A synchronous vector processor (SVP) (30) is provided to realize a horizontal decimation filter by processing in input value through a plurality of parallel processing elements (40). A plurality of input pixel values (80) representing a horizontal line of information in a video display are input to a data input register (DIR) (31) of the SVP (30). Each of the processing elements (40) is associated with a filter output and is operable to perform all calculations necessary to realize a multi-tap filter structure for the associated output. This is achieved by first increasing the frequency of the input signal by inserting zeros therein and then performing a number of multiplications and additions to generate an output value for that processing element, this realizing an interpolation FIR filter algorithm. The finite impulse response (FIR) filter algorithm is defined by predetermined filter coefficients stored in a constant generator (71d). Each of the processing elements are utilized to multiply a plurality of near-neighbor input values with FIR filter coefficients that are obtained from a constant generator (71d). The resulting sum for each of the processing elements is then input to the a data output register (DOR) (16) as the filter output. The output of the SVP (30) is then input to line memory (90) that is operable to decimate the output of select ones of the processing elements of the SVP (30). This rearranges the outputs to decrease the number of output pixels for each line relative to the number of input pixels for each line.

Programmable horizontal line filter implemented with synchronous vector

A Serial Video Processor (SVP) is provided for processing data through a plurality of parallel processing elements (228). Data is first stored in a data input register (DIR) (222) and then processed through the PE (228). The data is then output into a Data Output Register (DOR) (230). During one pass of data through the PE (228), a variable is calculated and stored in an auxiliary register (242). This auxiliary value is typically selected from one of the processing elements representing a value over the entire or part of the input vector of data. A multiplexer (248) selects this value from the output value stored in the register (242) and then inputs it to a second multiplexer (240). The second multiplexer (240) is operable to select either a predefined variable from either another auxiliary register (238) or from an instruction generator ROM (236), or select the precalculated variable stored in the register (242). When the variable in the register (242) is selected, it is globally spread over the entire PE ( 228) for utilization in a subsequent calculation. In the subsequent calculation, the data utilized to generate the variable was delayed to generate the variable and then utilize the variable in a present calculation.

Feedback register configuration for a synchronous vector processor

A constant generator is described which provides a sequence of digital constants in a synchronous vector processor. The constant generator includes a constant loop memory for storing data words organized into a plurality of data constant patterns and an end of loop bit, a constant loop counter for supplying sequential addresses to the constant loop memory, and a constant loop counter controller for loading the counter with one of a set of predetermined starting addresses associated with a desired constant pattern stored in the constant loop memory. Additionally, a method of supplying a sequence of digital constants in said constant generator is disclosed and includes the steps of storing a plurality of data words in a plurality of constant patterns, where each constant pattern includes an end of loop bit, supplying an address to the constant loop memory and supplying sequential addresses to the constant loop memory.

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Tokyo, Japan

Hiroshi Miyaguchi