Matsushita Electric Industrial Co., Ltd.

Nippon Electric Co., Ltd.

Hiroshi Minakuchi

Yoshio Tetsugu

Yoshiaki Igarashi

Kazuo Tokuda

Tsunemi Mitsui

Toshio Inaji

Hiromitsu Nakano

Tadashi Kunihira

Kazutsugu Kobayashi

Isao Yoshida

Tomio Oyama

Mitsuharu Ota

Masanobu Tsugita

Kunihira Tadashi

The invention provides a speed controller which detects the period of an AC signal containing information of the rotational speed of a motor and controls the rotational speed based on the detected period value and a reference speed value. More particularly, the speed controller computes the amount of the deviation of the AC signal based on continuously detected period values and the reference speed value, and then stores the computed deviation amount in a memory as a correction value. Using the correction value stored in the memory, the speed controller corrects the deviation of the period, and thus, the speed of the rotation of the motor can be controlled with extremely high precision.

Speed controller

A servo system for controlling the rotational speed of a rotating body or the moving speed of a moving body to be a desired speed. The system comprises a voltage source which generates at least two predetermined voltages, a comparator which compares a voltage of an AC signal containing a speed information of the moving body with each of the voltages generated by the voltage source and outputs at least two output signals in each half period of the AC signal, a counter for counting reference clock signals, a memory for storing a count value of the counter when the comparator outputs each of the output signals, a processor for producing a speed error signal from the count value stored in the memory, and a driver for supplying a driving power to the moving body in accordance with the speed error signal thereby to keep a desired speed of the moving body. Further, an error compensator may be provided for compensating a voltage shift of the predetermined voltages.

Servo system

A driving circuit for a brushless DC motor having a small amount of torque ripple comprises a magnetic pole position detecting circuit for detecting positions of magnetic poles of a rotor magnet and delivering polyphase signals indicating the positions, a rectifier adder circuit for producing a sum of positive or negative portions of the polyphase signals from the magnetic pole position detecting circuit, a first error amplifier for adjusting a gain of the magnetic pole position detecting circuit to make an output signal of the rectifier adder circuit to be proportional to an instruction signal, a power supply circuit for supplying currents to armature coils in response to the polyphase signals, a modulating signal producing circuit for producing a modulating signal synchronized with the rotation of the motor, and a second error amplifier for adjusting a gain of the power supply circuit to make the currents supplied to the armature coils to be proportional to the modulating signal.

Driving circuit for brushless DC motors

A binary counter consists of a plurality of unit stages each having a bistable circuit, a buffer circuit for generating an output corresponding to an output state of the bistable circuit, a switching circuit for supplying an output of the buffer circuit to the bistable circuit, and a coincidence gate for supplying a clock signal to the next unit stage in accordance with the predetermined output state of the bistable circuit.

Binary counter having buffer and coincidence circuits for the switched

An integrated precision reference source for supplying a reference voltage or a reference current under the condition of a lower feed voltage is disclosed, includes a first transistor, a first resistor connected between base and collector of the first transistor, a second resistor connected between base and emitter of the first transistor, and a second transistor whose base is connected to the collector of the first transistor and whose emitter is connected through a third resistor to the emitter of the first transistor.

Integrated precision reference source

A binary counter consists of some unit stages having a first pair of coincident gates composed of a first and a second coincident gates, a first input terminal of each being cross-coupled with the other's output terminal, and a second pair of coincident gates composed of a third and a fourth coincident gates, a first input terminal of each being cross-coupled with the other's output terminal.

Binary counter

A digital-to-analog conversion apparatus for converting a digital input value into an output signal having an active-level duration which varies analog-like depending on the input value. The apparatus consists of a binary counter and several decoding-gates, which thereby form a digital-to-analog conversion system which is simple in construction and has a high stability at high frequency.

Digital-to-analog conversion apparatus with a variable active-level

Disclosed is an integrated circuit in which more than two kinds of information outputs are superimposed on the same output terminal and the output level of an output terminal is varied in more than three steps in order to apply many information outputs to a small number of output terminals and transmit the operation state of the internal circuit externally. The structure of the integrated circuit is simplified, because the number of terminals in the integrated circuit and the number of connection wires between internal and external circuits can be reduced.

Integrated signal processing circuit

A programmable frequency divider includes a programmable counter which comprises flip-flops 1 to 11 of a number less by one than the number of bits in a program value. The divider has first and second control circuits 101, 102 which respectively control every half period of a preset divided output pulse alternately, the second control circuit acting to delay the moment of the control in response to the least significant bit having a selected logic level, thereby enabling one to reduce the clock pulse frequency to a half in comparison with a conventional one. One can also obtain an optional sub-output signal of twice or one-half the frequency of a preset frequency output signal. Refer to FIG. 2.

Programmable frequency divider

An input signal processing circuit formed as an integrated circuit is provided with power supply terminals of plus and minus potentials, a voltage dividing terminal connected to a voltage dividing point between the power supply terminals, and an input terminal applied thereto with an external operation signal. A discriminator circuit is included in the input signal processing circuit to determine whether a signal potential applied to the input terminal is above or below the divided voltage potential and to switch over an operating state of a circuit block contained within the input signal processing circuit to another operating state depending on the results of the determination.

Input signal processing circuit formed as an integrated circuit

A first frequency-to-voltage converter develops a first voltage representative of a standard frequency. A variable frequency source is provided to furnish a pulse sequence with constant-duration but variable repetition pulses. A frequency-to-voltage converter receives the pulse sequence to develop a second voltage representative of a total pulse energy generated in the pulse sequence per unit time. The deviation of the second voltage from the first voltage is detected by a comparator to control the variable frequency source to derive a desired frequency.

Frequency synthesizer

A digital frequency synthesizer comprises a programmable frequency divider, an analog-to-digital converter for converting an analog program control signal into a digital signal, and a digital storage medium for storing the digital signal to control the frequency division ratio of the programmable frequency divider in accordance with the digital value of the stored signal.

Digital frequency synthesizer with frequency divider programmable in

A programmable digital frequency divider comprises a programmable binary counter in receipt of an input pulse train to develop output pulses at a frequency variable as a function of a set of binary program control signals supplied in the form of normal binary number system. A binary code converter is provided to convert the binary number system of the program control signal into a modified binary number system in which the modified binary number is an integral multiple of the corresponding input binary number minus error compensating binary digits, wherein the number of compensating bits differs depending on the particular binary number. Electrical signals representing the modified binary numbers are supplied to the program input terminals of the binary counter so that the frequency of its output signal is substantially linearly variable as a function of discrete variations of the program control signal.

Programmable digital frequency divider for synthesizing signals at

A phase-locked loop system for controlling the speed of a motor or the like comprises an oscillator generating clock pulses or the like comprises a programmable frequency divider receptive of clock pulses for delivery of output pulses at a frequency which is an integral submultiple of the clock frequency, the integral submultiple being variable as a function of external supplied digital signals. A phase comparator compares speed related pulses. A transducer generates pulses at a repetition frequency related to the speed of the motor which is compared in the phase comparator with the output pulse from the frequency divider for driving the motor. A programmable binary counter is provided which is reset in response to the beginning of each period of the speed related pulses for counting the clock pulse. A logic gate circuit is connected to the counter stages of the programmable counter to define a range of pulse counts to generate motor control voltage signals when the count falls outside of the defined range.

Phase-locked loop speed control system using programmable counter for

A digital frequency-phase comparator includes a bistable element responsive to first and second frequency input pulse signals for generating a phase error signal, a circuit which includes second and third bistable elements responsive only to the leading edge transition of the input pulse signals in the presence of the outputs from the first bistable element to generate frequency error signals, and a circuit which combines the phase and frequency error signals to provide a triple state output.

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Shiga, Japan

Hiroshi Minakuchi