Nec Corporation

Chugai Seiyaku Kabushiki Kaisha

Institute for Advanced Skin Research Inc.

Hiroshi Matsushita

Yasushi Murakami

Masao Takahashi

Masuo Koizumi

Shun-Ichi Hata

Masamitsu Honda

Yukifumi Noda

Kazuo Sasahara

Hiroshi Nakakimura

Tomohiro Neichi

When a semiconductor integrated circuit device is reset, an input and output node is to be pulled down or up for stability of the integrated circuit, wherein a series combination of a pull-down resistor/pull-up resistor and a switching transistor is integrated on the semiconductor chip in such a manner as to permit the switching transistor to flow electric current through the pull-down/pull-up resistor only when the semiconductor integrated circuit device is reset, thereby enhancing the stability without sacrifice of the power consumption.

Circuit using internal pull-up/pull-down resistor during reset

An output logic setting circuit includes a fusible fuse element which is selectively rendered disconnected by external signal operation. The output logic setting circuit is designed to output, from an output terminal, a change in logic output state when the fuse element is rendered disconnected. The output logic setting circuit includes an inverter circuit which is arranged between the fuse element and the output terminal and which has a threshold set to ensure proper circuit operation even if the blown fuse element returns to an apparent connected state over time.

Output logic setting circuit in semiconductor integrated circuit

Microemulsion preparation containing a slightly absorbable substance

A full differential type analog circuit includes a full differential type operational amplifier, a first network, a second network, and a third network. The full differential type operational amplifier has inverting and non-inverting input terminals and inverting and non-inverting output terminals. The first network is connected between the inverting input terminal and the non-inverting output terminal and has a first input terminal for inputting a signal to the inverting input terminal and a first output terminal connected to the non-inverting output terminal. The second network is connected between the non-inverting input terminal and the inverting output terminal and has a second input terminal for inputting a signal to the non-inverting input terminal and a second output terminal connected to the inverting output terminal. The third network is connected between the first and second networks and includes two capacitors having the same arrangements, each formed by parallelly connecting an upper capacitor electrode and a lower capacitor electrode formed on a semiconductor substrate in opposite directions.

Full differential type analog circuit having parallel oppositely

Dibenzoxazepine derivatives of the formula: ##STR1## wherein R.sub.1, n, R.sub.2 and R.sub.3 are as defined in the description, process for preparing the same, pharmaceutical composition containing the same and method of treating diseases in circulatory organs administering the composition to a patient are disclosed. The compounds of the formula have lipid lowering activity, lipid peroxide lowering activity, blood sugar lowering activity and activity to inhibit the aggregation of platelets, and hence are useful as a medicine.

Dibenzoxazepine derivative, and pharmaceutical composition comprising

Growing community of inventors

Tokyo, Japan

Hiroshi Matsushita