Oki Electric Industry Co., Ltd.

Oki Electric Co., Ltd.

Hiroshi Kuwabara

Shooji Kitazawa

Teruhiro Harada

A method of operating an EPROM which has a word line, a predecode circuit having an ou tput terminal and a transistor having a first electrode connected to the output terminal of the predecode circuit, a second electrode connected to a word line and a control gate. The method of operating the EPROM includes generating a selection signal and an inverted signal thereof in accordance with an internal address signal, and generating a delayed signal responsive to the selection signal and the inverted signal so that the delayed signal rises by a predetermined time delay behind a rising of the selection signal and rapidly falls substantially simultaneously with a rising of the inverted signal. Thereafter the potential of the selection signal is boosted in accordance with a potential of the delayed signal and the boosted selection signal is supplied to the control gate of the transistor connected between the predecode circuit and the word line.

Method of operating an EPROM including delaying and boosting steps

Am EPROM system comprising a memory cell array formed of a matrix of non-volatile semiconductor memory cells, each having a control gate and a floating gate, and storing electric charges on the floating gate, and a word line drive circuit driving respective word lines connected to the control gates of the respective memory cells. The word line drive circuit comprises a delay circuit for delaying a first selection signal, a boosting capacitor having a first electrode connected to the first selection signal and a second electrode connected the output of the delay circuit, and MOS transistors each having a gate electrode connected the second electrode of the boosting capacitor, a first electrode connected to receive a second selection signal and a second electrode connected to a word line.

Erasable and programmable read-only memory system

In a current sense circuit for detecting a read current from a selected memory cell in a memory cell matrix of a ROM, each of a first series circuit and a second series circuit comprises: a current supply means having a first main electrode connected to a power supply; a first MOS FET having a first main electrode connected to the second main electrode of the current supply means; and a second MOS FET having a first main electrode connected to the second main electrode of the first MOS FET, a second main electrode connected to a second power supply, and a gate electrode connected to the first main electrode of the first MOS FET. The gate electrode of the first and the second MOS FETs of the reference voltage generator are connected together; the gate electrodes of the first MOS FETs of the first and second series circuits are connected together; and the ratio of the current driving capability between the first MOS FET of the first series circuit and the first MOS FET of the second series circuit is substantially equal to the ratio of the current driving capability between the second MOS FET of the first series circuit and the second MOS FET of the second series circuit.

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Tokyo, Japan

Hiroshi Kuwabara