Mitsubishi Denki Kabushiki Kaisha

Hiroshi Kuranaga

Kouji Gotou

Takeo Nakabayashi

Harufusa Kondou

Satoshi Sugawa

A plurality of frames constituting a screen are divided into a plurality of groups such as G through G The number of pixels per line is made different between any adjacent two of these groups in such a manner that all lines included in each group will have the same number of pixels each. There should be a plurality of groups such as G through G which exclude lines having active pixels corresponding to image portions. Lines through having active pixels may have the same number of pixels each. The number of pixels per line is allowed to be different by 1 between any adjacent two of the groups.

Semiconductor integrated circuit

Data received from a first layer is processed in a communication processor. Memory controller determines whether or not an instruction to be processed next by a processing circuit is stored in an internal RAM. When it is stored, it reads the instruction from internal RAM, and otherwise, it reads an instruction from an external ROM through an DMAC. Processing circuit changes setting of register values in respective registers in memory controller to values of the corresponding layer, when processing for one layer is completed. Consequently, the layer to be processed by the communication processor is switched.

Communication processor

A transmitter/receiver applicable as an interface circuit in ISDN terminals is disclosed. In externally designated total phase deviation measurement mode, the delay time caused by a receiver circuit and a driver circuit, i.e. a phase difference, is predetected by a phase comparator. The detected phase difference signal is stored in a phase control circuit, and the phase control circuit controls the pahse of a periodical timing signal generated from a PLL circuit. Therefore, as a data buffer applies a transmitting data to the driver circuit 7 in response to the phase control timing signal, the phase difference of the transmitting data signal generated from the driver circuit relative to the received data signal is made to be the minimum.

Transmitter/receiver for generating transmitting data signal in

There are disclosed an FCS encoder responsive to data to be transmitted for generating a frame check sequence (FCS) code to check a transmission error, and an FCS decoder for detecting an error. These FCS encoder and FCS decoder have a division circuit and a multiplication circuit each of which comprises shift registers in 16 stages and EXOR gates. Since there is no need for logical elements to be connected between the respective shift registers, this FCS encoder can be constituted to show a regular circuit layout on a semiconductor substrate.

Error check code generating device and transmission error detecting

Programmable Logic Array PLA) cells are arranged at intersections of input lines and output lines of the array. Particular PLA cells to be programmed are arbitrarily selected by word line and bit line decoders. Switches for programming the PLA cells to implement a desired logic function are controlled by data stored in a random access memory whereby programming of the PLA can be changed arbitrarily and during operation of a system including the PLA.

Growing community of inventors

Hyogo, Japan

Hiroshi Kuranaga