Mitsubishi Materials Silicon Corporation

Mitsubishi Denki Kabushiki Kaisha

Hiroshi Koya

Hisashi Furuya

Takaaki Shiota

Yoji Suzuki

Yukio Muroi

Hideo Tanaka

Yoshinobu Nakada

Yasuhiro Kimura

Hidekazu Yamamoto

Tomonori Yamaoka

Kazuhito Matsukawa

Yoshihisa Nonogaki

Jun Furukawa

Etsuro Morita

Hiroshi Shinyashiki

Yuji Nakata

A method of heat-treating a silicon wafer has the steps of: preparing a silicon wafer having an oxygen concentration of 1.2&times;10 atoms/cm or less (old ASTM) without generating crystal originated particles(COP'S) and interstitial-type large dislocation(L/D); forming a polysilicon layer of 0.1 &mgr;m to 1.6 &mgr;m in thickness on a back of the silicon wafer by a chemical-vapor deposition at a temperature of 670&deg; C.&plusmn;30&deg; C.; and heat-treating the silicon wafer having the polysilicon layer in an oxygen atmosphere at 1000&deg; C.&plusmn;30&deg; C. for 2 to 5 hours and subsequently at 1130&deg; C.&plusmn;30&deg; C. for 1 to 16 hours. In this method, the silicon wafer before the formation of the polysilicon layer thereon is the type of a wafer in which oxidation induced stacking faults(OSF's) manifest itself at a center of the wafer when the wafer is subjected to the heat-treatment. Accordingly, the resulting silicon wafer with a polysilicon layer is of OSF fee and COP free, even when the wafer is subjected to the conventional OSF-manifesting heat treatment. The wafer with the polysilicon layer exerts a uniform gettering effect between the peripheral edge and center of the silicon wafer as a result of a uniform oxygen precipitation occurred at the entire surface of the silicon wafer.

Silicon wafer, and heat treatment method of the same and the heat-treated silicon wafer

An ingot is manufactured by pulling it up such that V/Ga and V/Gb become 0.23 to 0.50 mm /minute &deg; C., respectively, where V (mm/minute) is a pulling-up speed, and Ga (&deg; C./mm) is and axial temperature gradient at the center of the ingot and Gb (&deg; C./mm) is an axial temperature gradient at the edge of the ingot at temperatures in a range of 1,300&deg; C. to a melting pointy of silicon. A wafer obtained by slicing the ingot is heat treated in a reductive atmosphere at temperature in a renge of 1,050&deg; C. to 1,220&deg; C. for 30 to 150 minutes. A silicon wafer free of OSF's, free of COP's, and substantially free of contamination such as Fe and of occurence of slip, is obtained.

Silicon wafer, and manufacturing method and heat treatment method of the same

A substrate having a surface on which silicon is epitaxially grown; wherein the substrate is cut from an oxygen induced stacking fault generation area of a single crystal silicon rod grown by the Czochralski method.

Substrate for epitaxial growth

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Tokyo, Japan

Hiroshi Koya