Nec Corporation

Hitachi, Ltd.

Hiroshi Kotaki

Hideki Tanaka

Takaaki Suzuki

Motomune Kodama

Yasukazu Inoue

Shigeho Tanigawa

Kazuya Nishi

Shozo Nishimoto

The purpose of the present invention is to provide a method for causing sufficient deformation in precursor particles even when a soft high-purity metal is used for an outer layer material in mechanical milling, and manufacturing an MgBsuperconducting wire. A method for manufacturing an MgBsuperconducting wire in which an MgBfilament is covered by an outer layer material, the method comprising: subjecting magnesium powder and boron powder to a shock that is insufficient for MgBto be clearly produced, and producing precursor particles in which boron particles are dispersed inside a magnesium matrix; filling a metal tub with the precursor particles; processing the metal tube filled with precursor particles to form a wire; and heat-treating the wire to synthesize the MgB; wherein the method is characterized in that a portion of the wire-drawing step includes swaging.

MGB2 superconducting wire material and manufacturing method therefor

The present invention is intended to increase the critical current density of a wire rod having a shape with good symmetry such as a round wire or a square wire by making use of mechanical milling method. The production method of the present invention for the MgBsuperconducting wire rod comprises a mixing process of preparing a powder by adding a solid organic compound to a magnesium powder and a boron powder and then applying an impact to the powder to prepare a mixture of the powder in which boron particles are dispersed inside magnesium particles, a filling process of filling a metal tube with the mixture, an elongation process of elongating the metal tube filled with the mixture and a heat treatment process of heat-treating the metal tube to synthesize MgB.

Production method for MgBsuperconducting wire rod superconducting coil and MRI

A semiconductor memory device having an improved storage capacitor is disclosed. The memory device comprises a dynamic memory cell which including a gating transistor having first and second semiconductor regions formed on a surface of a semiconductor substrate and opposite in conductivity type to the semiconductor substrate, a gate insulating layer formed on the surface of the substrate between the first and second regions, a gate formed on the gate insulating layer and a first insulating layer covering the surface of the gate, and a storage capacitor having a second insulating layer thicker than the first insulating layer and formed on the surface of the semiconductor substrate via the first insulating layer, the second insulating layer having a trench exposing the surface of first region, a first conductive layer formed on the side wall of trench of the second insulating layer and connected to the first region, a dielectric insulating layer formed on the first conductive layer and a second conductive layer formed on the dielectric insulating layer.

Semiconductor memory device having improved dynamic memory cell structure

For making an inter-level insulating film between a capacitor electrode and a gate electrode mild at the shoulder portion thereof, a doped polysilicon film is overlain by a silicon oxide film on a dielectric film structure, and the silicon oxide film is slightly etched through an isotropical technique by using a mask layer for forming a hollow space with a generally quarter-circle configuration beneath the mask layer, then anisotropically etching the silicon oxide and the doped polysilicon by using the same mask layer, then depositing silicon oxide on the entire surface, then exposing the surface of a semiconductor substrate by using an etch-back technique for leaving the inter-level insulating film on the capacitor electrode, then forming a gate electrode on the inter-level insulating film. Since a declining shoulder portion takes place at the upper end of the silicon oxide film due to the isotropical etching, the inter-level insulating film and, accordingly, the gate electrode smoothly extend over the capacitor electrode, and, for this reason, the gate electrode is free from undesirable disconnection.

Process of fabricating dynamic random access memory cell

A method for fabricating a semiconductor memory device which includes a single substrate, at least one memory cell including at least one MOS transistor formed on the single substrate, and a peripheral circuit having at least one MOS transistor formed on the single substrate, comprises the steps of forming on the single substrate a gate electrode for each of the MOS transistors of the memory cell and the peripheral circuit, iono-implanting impurities at a low dosage by using the gate electrodes as a mask so as to forming a low impurity concentration of source/drain regions of the MOS transistors of the memory cell and the peripheral circuit, depositing a mask layer to cover an area of the memory cell, and ion-implanting impurities at a high dosage by using the mask layer as a mask, so as to dope impurities to only the source/drain regions of the MOS transistor of the peripheral circuit, so that the MOS transistor of the memory cell has the source/drain regions of a low impurity concentration, and the MOS transistor of the peripheral circuit has the source/drain regions including a high impurity concentration portion.

Method for fabricating semiconductor memory device

A dynamic random access memory device including one-transistor type memory cells each having a trench capacitor is disclosed. An impurity region of a conductivity type opposite to the substrate and having a net-like plane shape is provided in an inner portion of the substrate, and the impurity region is led-out at a part to the major surface of the substrate. A trench is formed in the substrate from the major surface into the impurity region so that a wall section of the trench is constituted by the impurity region. A dielectric film of the capacitor is formed on the wall section, and a capacitor electrode is formed on the dielectric film and connected to source or drain region of the transistor.

Growing community of inventors

Tokyo, Japan

Hiroshi Kotaki