Hitachi, Ltd.

Hitachi Computer Electronics Co., Ltd.

Hiroshi Kosuge

Yoshio Kiriu

Ryoichi Kurihara

Eiji Fujiwara

Junichi Taguri

Kazuya Iwasaki

Shigeru Kaneko

An error detecting and correcting apparatus includes a unit for receiving an encoded word including a plurality of b-bit bytes (b is an integer not less than two) and generating syndrome from the encoded word according to a first parity check matrix H.sub.1, and a unit for correcting errors in the received encoded word based on the syndrome.

Error detecting and correcting method and system

Memory expansion using memory packages of different generations is performed without unnecessarily increasing the minimum memory capacity of a memory device and while obtaining a high error detecting ability and high reliability. In expanding the capacity of a memory device by using first generation 1M.times.1 bit IC memory packages, second generation 4M.times.4 bits IC memory packages, or third generation 16M.times.8 bits IC memory packages, the total code length is set to 40 bits, a 4's multiple, within a range longer than the total code length necessary for S4ED and shorter than the total code length necessary for S8ED, and a reduced code is used for enhancing the S8ED function. In this manner, wasteful first generation IC memory packages can be reduced in number, and the error detecting ability of a memory device using third generation memory packages can be retained substantially the same as that of a memory device using first generation memory packages.

Data error correcting/detecting system and apparatus compatible with

An error detecting apparatus in which an error within an arbitrary and continuous (b-1) bit block is detected using a SEC-DED-SbED code. The (b-1) bit block is any continuous (b-1) bit block within an information consisting of several b bit blocks. The data are encoded by using a power of a matrix C, defined as: ##EQU1## and a matrix B. Matrix B is comprised by arbitrarily replacing the rows and columns of the power of C matrix with row vectors from a set of (b+1) vectors: ##EQU2## The partial matrices obtained from matrices B and C are used to construct a parity matrix. Syndromes are computed from the information and the party matrix to detect errors.

Error detection system

A data transmission control device for controlling the data transfer between two memory means on the basis of an instruction from a processor is disclosed in which the instruction from the processor is decoded, a transfer request is issued to each memory means a plurality of times, depending upon a transfer unit indicated by the decoded instruction and an access unit of each memory means, a data buffer is provided between the memory means to temporarily store data whichis transferred from one of the memory means to the other memory means, and the issue of a transfer request to each memory means is allowed or stopped in accordance with the quantity of data stored in the data buffer.

Data transmission control device for controlling transfer of large

A method for correcting and detecting errors using the SEC-DED-SbED code is provided, wherein the information consisting of several blocks of b bits is encoded based on the parity matrix including any of b.times.b matrix X q (q=1 to b) in which each row of b.times.b matrix ##EQU1## is cyclically displaced along the column direction by a desired number (q) of bits in each partial matrix corresponding to the above block.

Growing community of inventors

Hadano, Japan

Hiroshi Kosuge