Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Hiroshi Kono

Takashi Shinohe

Takuma Suzuki

Teruyuki Ohashi

Johji Nishio

Makoto Mizukami

Shunsuke Asaba

Masaru Furukawa

Takahiro Ogata

Tatsuo Shimizu

Chiharu Ota

Souzou Kanie

Yoichi Hori

Shigeto Fukatsu

Kazuto Takao

Katsuhisa Tanaka

Atsuko Yamashita

Tomohiro Nitta

Ryosuke Iijima

Yujiro Hara

Ryoichi Ohara

Yukio Nakabayashi

Takao Noda

Takuo Kikuchi

Tsuyoshi Oota

Hiroyuki Irifune

Kohei Morizuka

Shuji Kamata

Kei Tanihira

Sozo Kanie

Yuji Kusumoto

Masanori Nagata

A semiconductor device according to an embodiment includes a transistor region and a diode region. The transistor region includes a first silicon carbide region of n-type having a first portion in contact with a first plane, a second silicon carbide region of p-type, a third silicon carbide region of n-type, and a gate electrode. The diode region includes the first silicon carbide region of n-type having a second portion in contact with the first plane and a fourth silicon carbide region of p-type. The semiconductor device includes a gate wiring electrically connected to the gate electrode. A distance between a high-concentration portion included in the fourth silicon carbide region and the gate wiring is larger than a distance between a high-concentration portion included in the second silicon carbide region and the gate wiring.

Semiconductor device, inverter circuit, driving device, vehicle, and elevator

A semiconductor device includes: a first conductive type first silicon carbide region including a first region, a second region and a third region both on the first region, the second region having impurity concentration equal to or higher than the first region, and the third region having impurity concentration higher than the second region; a second conductive type second silicon carbide region on the first silicon carbide region, the second silicon carbide region including a fourth region in contact with the second region and a fifth region in contact with the third region, and the fifth region having impurity concentration higher than the fourth region; a third silicon carbide region of a first conductive type on the second silicon carbide region; a first gate electrode; a first electrode having a first portion in contact with the second silicon carbide region and the third silicon carbide region; and a second electrode.

Silicon carbide semiconductor device with improved avalanche resistance

A semiconductor device of an embodiment includes a trench in a silicon carbide layer and extending in a first direction, a gate electrode in the trench, first, second, third and fourth silicon carbide regions disposed in the silicon carbide layer in the first direction in this order, first and third silicon carbide regions having first conductive type, second and fourth silicon carbide regions having second conductive type, fifth, sixth, seventh and eighth silicon carbide regions disposed in the silicon carbide layer in the first direction in this order above the first to fourth silicon carbide regions, fifth and seventh silicon carbide regions having first conductive type higher than first and third silicon carbide regions, sixth and eighth silicon carbide regions having second conductive type higher than second and fourth silicon carbide regions, a ninth silicon carbide region of a first conductive type above the fifth to eighth silicon carbide regions.

Semiconductor device

A semiconductor device according to an embodiment includes a semiconductor chip having a transistor region and a diode region, and a conductor. The semiconductor chip includes a first electrode, a second electrode, a silicon carbide layer between the first electrode and the second electrode, and a gate electrode. The first electrode includes a first region in the transistor region and a second region in the diode region. A first contact area between the conductor and the first region is larger than a second contact area between the conductor and the second region.

A semiconductor device of embodiments includes: a first silicon carbide region of first conductive type including a first region in contact with a first face of a silicon carbide layer having first and second faces; a second silicon carbide region of second conductive type above the first silicon carbide region; a third silicon carbide region of second conductive type above the second silicon carbide region; a fourth silicon carbide region of first conductive type above the second silicon carbide region; a first gate electrode and a second gate electrode extending in the first direction; a first electrode on the first face and including a first portion and a second portion between the first and the second gate electrode. The first portion contacts the third and the fourth silicon carbide region. The second portion provided in the first direction of the first portion and contacts with the first region.

A semiconductor device includes a first electrode, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a second electrode. The fourth semiconductor layer is located in a second region on the first semiconductor layer. The fourth semiconductor layer is separated from the second semiconductor layer with a portion of the first semiconductor layer interposed. An impurity concentration of the fourth semiconductor layer is greater than an impurity concentration of the first semiconductor layer and less than an impurity concentration of the second semiconductor layer.

A semiconductor device of an embodiment includes a transistor region and a diode region. The transistor region includes an n-type first silicon carbide region having a first portion in contact with a first plane, a p-type second silicon carbide region, an n-type third silicon carbide region, a first electrode in contact with the first portion, the second silicon carbide region, and the third silicon carbide region, a second electrode in contact with a second plane, and a gate electrode. The diode region includes an n-type first silicon carbide region having a second portion in contact with the first plane, a p-type fourth silicon carbide region, a first electrode in contact with the second portion and the fourth silicon carbide region, and a second electrode. An occupied area per unit area of the fourth silicon carbide region is larger than an occupied area per unit area of the second silicon carbide region. The first diode region is provided between a first transistor region and a second transistor region.

Semiconductor device, inverter circuit, drive device, vehicle, and elevator

A semiconductor device of embodiments includes: an element region including a transistor and a first diode; a termination region surrounding the element region and including a second diode; and an intermediate region between the element region and the termination region. The element region includes a first electrode, a second electrode, a gate electrode, a silicon carbide layer, and a gate insulating layer. The termination region includes a first wiring layer electrically connected to the first electrode, the second electrode, and the silicon carbide layer. The intermediate region includes a gate electrode pad, a first connection layer electrically connecting the first electrode and a part of the first wiring layer, a second connection layer electrically connecting the first electrode and another part of the first wiring layer, a second wiring layer electrically connected to the gate electrode pad and the gate electrode, and the silicon carbide layer.

A semiconductor device of embodiments includes: an element region including a transistor, a first diode, and a first contact portion; a termination region surrounding the element region and including a second contact portion; and an intermediate region provided between the element region and the termination region and not including the transistor, the first diode, the first contact portion, and the second contact portion. The element region includes a first electrode, a second electrode, a gate electrode, a silicon carbide layer, and a gate insulating layer. The termination region includes a first wiring layer electrically connected to the first electrode, the second electrode, and the silicon carbide layer. The intermediate region includes the silicon carbide layer. The width of the intermediate region in a direction from the element region to the termination region is equal to or more than twice the thickness of the silicon carbide layer.

A semiconductor device includes a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type on the first region, and a third silicon carbide region of a second conductivity type on the second region. Fourth and fifth silicon carbide region of the first conductivity type are on the third region. A first electrode has a first portion between the fourth region and fifth region in a first direction. A metal silicide layer is between the first portion and the third region, between the first portion and the fourth region in the first direction, and between the first portion and the fifth silicon carbide region in the first direction.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device of embodiments includes: a first electrode; a second electrode; a gate electrode extending in a first direction; and a SiC layer. The SiC layer includes: a first conductive type first SiC region having a first region, a second region facing the gate electrode, and a third region in contact with the first electrode; a second conductive type second SiC region between the second region and the third region; a second conductive type third SiC region, the second region interposed between the second SiC region and the third SiC region; a second conductive type fourth SiC region, the third region interposed between the second SiC region and the fourth SiC region; a first conductive type fifth SiC region; a second conductive type sixth SiC region between the first region and the second SiC region; and a second conductive type seventh SiC region between the first region and the second SiC region and distant from the sixth SiC region in the first direction.

A semiconductor device of embodiments includes: a first electrode; a second electrode; a gate electrode extending in a first direction; a silicon carbide layer between the first electrode and the second electrode and including a first silicon carbide region of a first conductive type having a first region facing the gate electrode and a second region in contact with the first electrode, a second silicon carbide region of a second conductive type, and a third silicon carbide region of a second conductive type, the first region being interposed between the second silicon carbide region and the third silicon carbide region. A first width of the first region in a second direction perpendicular to the first direction is 0.5 μm or more than and 1.2 μm or less. A second width of the second region in the second direction 0.5 μm or more than and 1.5 μm or less.

A semiconductor device of embodiments includes a first gate electrode, a second gate electrode, a third gate electrode extending in a first direction, and a gate wiring line extending in a second direction crossing the first direction and to which the first to the third gate electrodes are connected. Assuming distance between the first and the second gate electrode in the second direction in a first region is S1, distance between the first and the second gate electrode in the second direction in a second region closer to the gate wiring line than the first region is S2, distance between the second and the third gate electrode in the second direction in the first region is S3, and distance between the second and the third gate electrode in the second direction in the second region is S4, following Expressions are satisfied,1&#x3c;3,1&#x3c;2,3&#x3e;4.

According to an embodiment, provided is a semiconductor device includes a semiconductor layer; a first electrode; a second electrode; an electrode pad; a wiring layer electrically connected to the gate electrode; a first polycrystalline silicon layer electrically connected to the electrode pad and the wiring layer; and an insulating layer provided between the first polycrystalline silicon layer and the electrode pad and between the first polycrystalline silicon layer and the wiring layer and having a first opening and a second opening. The electrode pad and the first polycrystalline silicon layer are electrically connected via an inside of the first opening. The wiring layer and the first polycrystalline silicon layer are electrically connected via an inside of the second opening, A first opening area of the first opening is larger than a second opening area of the second opening.

A semiconductor device of embodiments includes a silicon carbide layer including an element region and a termination region around the element region, the termination region having first straight-line portions extending in a first direction, second straight-line portions extending in a second direction, and corner portions between the first straight-line portions and the second straight-line portions, the termination region including a second-conductivity-type second silicon carbide region having a dot-line shape with first dot portions and first space portions surrounding the element region, an occupation ratio of the first dot portions is larger in the corner portions than in the first straight-line portions, and a second-conductivity-type third silicon carbide region having a dot-line shape with second dot portions and second space portions surrounding the second silicon carbide region, an occupation ratio of the second dot portions is lager in the corner portions than in the first straight-line portions.

Growing community of inventors

Kanagawa, Japan

Hiroshi Kono