Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Vlsi Engineering Corp.

Hiroshi Kawamoto

Katsuhiro Shimohigashi

Hiroo Masuda

Kunihiko Ikuzaki

Kazumasa Yanagisawa

Katsuyuki Sato

Yoshiaki Onishi, Deceased

Takashi Shinoda

Masahiro Ogata

Miki Matsumoto

Kikuo Sakai

By Junko Onishi, Administratrix

Kazuhiko Kajigaya

Masashi Horiguchi

Masakazu Aoki

Kazuyuki Miyazawa

Hitoshi Tanaka

Jun Etoh

Tsugio Takahashi

Yasunori Yamaguchi

Nobuyoshi Tanimura

Tokumasa Yasui

Shigeki Ueda

Junko Onishi, Administratrix

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Semiconductor memory

Semiconductor Memory

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed irk the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

A voltage limiter circuit is disposed in a semiconductor IC chip in order to reduce an operating voltage of an internal circuit of a scaled-down element. A small capacitance of a Vcc wiring by the disposition constitutes a resonance circuit together with an inductance of the Vcc wiring. Resonance at the resonance circuit causes large variation of a supply current and noise. An additional capacitance is connected between the Vcc wiring and a Vss wiring in order to suppress the variation and noise. The capacitance is formed by a PN junction and is connected in series to a damping resistance.

Semiconductor integrated circuit having voltage limiter circuit

The present invention disposes a redundancy logic device and a redundancy line which are used selectively in place of a logic device or a line, which becomes unusable, in a logic portion of a semiconductor integrated circuit device such as a gate array integrated circuit.

Single chip IC device having gate array or memory with gate array and

A semiconductor integrated circuit which has the function of self-checking defective bits, and which informs the exterior of its status when it has reached the status incapable of self-repair due to the limitation of the storage capacity of hardware for repairing the defective bits.

Semiconductor integrated circuit having self-check and self-repair

A voltage generating circuit having a voltage dividing circuit of complementary MISFETs is provided in an arrangement wherein a controlled output voltage, such as a bias voltage applied to plate electrodes of storage cells in a RAM, is obtained. The voltage dividing circuit has a series arrangement, between the power source voltage and a predetermined voltage, such as ground potential, of a first resistance, a first diode-connected MISFET, a second resistance and a second diode connected MISFET. Also, the voltage generator circuit has a first output MISFET of a first channel conductivity type having its gate coupled to the common connection of the first diode-connected MISFET and first resistance as well as a second output MISFET of the second conductivity type in series therewith which has a gate coupled to the common connection of the second diode-connected MISFET and second resistance. The first and second output MISFETs have their drains respectively coupled to receive the power source voltage and predetermined voltage and the source of the first output MISFET is coupled with the source of the second output MISFET wherein an output voltage of about 1/2 the potential of the power source voltage is obtained.

Complementary MISFET voltage generating circuit for a semiconductor

A dynamic RAM is provided with a plurality of 1-MOSFET memory cells, each having a storage capacitor and a switching MOSFET coupled to one electrode of the storage capacitor. The other electrode of each of the storage capacitors is coupled to a switching circuit which controls the voltage which is applied to the capacitor. The switching circuit is, in turn, coupled to both a voltage generating circuit (which preferably provides a voltage of 1/2 Vcc) and a voltage supply circuit which is set to provide predetermined test voltages. Thus, by operating the switching circuit, a voltage of 1/2 Vcc can be applied to the memory cell capacitors during normal operation of the dynamic RAM, and the predetermined test voltages can be applied to the memory cell capacitors during a testing operation.

Selective application of voltages for testing storage cells in

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed to a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

A protective circuit consisting of a resistor and MOSFET in a diode form and a switching element are connected to a bonding pad in order to prevent destruction of an internal circuit consisting of one or more MOSFETs. The switching element may consist of a parasitic MOSFET whose source and drain regions are formed by well regions. One of the well regions is connected to a semiconductor region as a guard ring.

Semiconductor device

A semiconductor memory includes a dummy cell for forming a reference potential, a read-only memory cell, and a differential amplifier circuit which receives the reference potential formed by the dummy cell and a signal read out from the memory cell. The differential amplifier circuit is dynamically operated so that the semiconductor memory is made smaller in power consumption and size than conventional units. Moreover, in order to reduce the power consumption, the memory cell is brought into the nonselection state when a predetermined time has passed after being selected. In addition, the semiconductor memory is provided with a compensating circuit in order to make the value of the capacitance connected to a word line for transmitting a selecting signal to the memory cell and the value of the capacitance connected to a dummy word line for transmitting a selecting signal to the dummy cell substantially equal to each other. Thus, the changes in potential of both the selecting signals are made substantially equal to each other. Accordingly, it is possible to reduce malfunctions.

Growing community of inventors

Kodaira, Japan

Hiroshi Kawamoto