Other

Renesas Technology Corp.

Hitachi, Ltd.

Hitachi Microcomputer System, Ltd.

Hiroshi Kawakubo

Ryosuke Kimoto

Hiroshi Koyama

Ryo Haruta

Hisao Nakamura

Seiichi Ichihara

Takashi Kikuchi

Takafumi Nishita

Takashi Miwa

Shiro Yamashita

Masanori Shibamoto

Chikako Imura

Masaru Kawakami

Yoichi Abe

For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.

Semiconductor device

In order to inhibit the connection failure due to the degradation of the connection interface strength of the electrode pad and the warp thereof in the semiconductor device having an electrode pad, a metal layer formed on the electrode pad, and a metal bump formed on the metal layer, in the present invention, gold (Au) is contained in the metal layer, the metal bump is made of solder mainly made of Sn and designed to have an average height H of 100 &#x3bc;m or less per unit area in the electrode pad, and the concentration of Au of the metal layer dissolved in the solder is set to 1.3&#xd7;10(Vol %) or less. More preferably, the metal bump contains palladium (Pd), and the solder coating for forming the metal bump on the electrode pad is performed by using the dipping and the paste printing in combination.

Semiconductor device having a particular electrode structure

The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads are arranged on one side opposite to the side on which bonding pads (effective pins) are arranged in the semiconductor chip. Dummy leads are formed on an insulating tape The semiconductor chip is supported with inner lead portions connected to the corresponding bonding pads and the inner lead portions of the dummy leads connected to the corresponding dummy pads

Semiconductor device and process for producing the same

The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads,are arranged on one side opposite to the side on which bonding pads (effective pins),are arranged in the semiconductor chip. Dummy leads,are formed on an insulating tape,The semiconductor chip is supported with inner lead portions,connected to the corresponding bonding pads,and the inner lead portions,of the dummy leads,connected to the corresponding dummy pads

The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.

Growing community of inventors

Fussa, Japan

Hiroshi Kawakubo