Bristol-myers Company

Renesas Electronics Corporation

Hitachi-high-technologies Corporation

Kabushiki Kaisha Kobe Seiko Sho

Semiconductor Technology Academic Research Center

Nec Corporation

Kobe Steel, Ltd.

The University of Tokyo

Other

Sony Corporation

Nippon Oil Fats Co., Ltd.

Tokyo Medical and Dental University

Rohm Co., Ltd.

The Furukawa Electric Co., Ltd.

Nec Electronics Corporation

Hiroshi Kawaguchi

Masataka Konishi

Takeo Miyaki

Koji Tomita

Hiroshi Tsukiura

Yasuhiro Okamoto

Hironobu Miyamoto

Tatsuo Nakayama

Kozo Nakamura

Kazuhiko Ishihara

Masahiko Yoshimoto

Toru Moro

Yoshio Takatori

Hiroaki Ohkuma

Masayuki Kyomoto

Koko Sugawara

Tomohiro Konno

Shintaro Izumi

Takayuki Nagai

Toshiyuki Takewaki

Yoshinao Miura

Shinichi Miyake

Hirofumi Fujii

Kyoichiro Saitoh

Ichiro Masumoto

Nobuhiro Nagura

Noboru Yamawaki

Yasutaka Onodera

Masaharu Sibata

Masaaki Kubo

Takashi Inoue

Takayasu Sakurai

Takehiro Ueda

Hiroshi Tamagaki

Osamu Tenmyo

Atsushi Mitsuzawa

Takao Okuda

Shinichi Harada

Masami Hatori

Tatsuo Nagamatsu

Kunihiko Tsuji

Kenichiro Minagawa

Yoshiharu Tanizaki

Koji Hanaguri

Katuhiko Shimojima

Yasuhiko Iwasaki

Tsutomu Teranishi

Kunitoshi Shimizu

Takeshi Suzuki

Katsuhiko Shimojima

Toshihiro Konishi

Takashi Tsuno

Hirofumi Sasaki

Shunsuke Okumura

Fumiki Asano

Minori Noguchi

Masahiro Kimura

Takahiro Jingu

Hiroshi Fujimoto

Shigeya Tanaka

Masami Makuuchi

Kei Shimura

Kenji Aiko

Yoichi Inoue

Mitsuaki Tsunakawa

Tomoo Nakayama

Yasuko Aoki

Kazuhiko Sanada

Isami Sakai

Takeshi Nizuka

Tomiharu Matsushita

Kouji Yamamoto

Fumihide Sakai

Toshiaki Hashizume

Masamichi Abe

Atsushi Yamamoto

Minoru Hanada

Tomohiro Hirai

Shigezo Kawakami

Homare Nomura

Makoto Kondo

Atsushi Tsuboi

Shuji Kusumoto

Robert Saliba Fayez

Kazuhide Tsuchiya

Kohei Onizuka

Riki Mizuno

Toshiki Igarashi

Tetsuya Kageyama

Hiroyuki Washio

Masamitsu Nakatani

Atsushi Umaki

Toshiya Kido

Kei-Ichi Fujisawa

Ippei Shiode

Kei-ichi Fujisawa

Hiroshi Takechi

Hiroaki Takadama

A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.

Semiconductor device and method of manufacturing semiconductor device

The present invention makes it possible to improve the characteristic of a semiconductor device using a nitride semiconductor. An electrically-conductive film is formed above a gate electrode above a substrate with an interlayer insulation film interposed and a source electrode coupled to a barrier layer on one side of the gate electrode and a drain electrode coupled to the barrier layer on the other side of the gate electrode are formed by etching the electrically-conductive film. On this occasion, the source electrode is etched so as to have a shape extending beyond above the gate electrode to the side of the drain electrode and having a gap (opening) above the gate electrode. Successively, hydrogen annealing is applied to the substrate. In this way, by forming the gap at a source field plate section of the source electrode, it is possible to efficiently supply hydrogen in the region where a channel is formed in the hydrogen annealing process.

Manufacturing method of semiconductor device and semiconductor device

Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.

Semiconductor device and method of manufacturing the semiconductor device

A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (&#x3b8;1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed.

Semiconductor device and method for manufacturing the same

A log analysis system includes a first processor unit, a second processor unit, a third processor unit, and a fourth processor unit. The first processor unit normalizes the detection log acquired by an acquirer, allocating the detection log into predefined monitoring target units, and outputs the monitoring target units. The second processor unit appends common information based on a predefined rule to each of the monitoring target units of the detection log output from the first processor unit, arranges the monitoring target units into information granularities based on the content of the detection log and common information, and outputs the monitoring target units as analysis unit information. The third processor unit gathers the analysis unit information output from the second processor unit and setting detection target event candidates based on a predefined rule, and outputs the detection target event candidates and the determination results.

Log analysis system

In a semiconductor device using a nitride semiconductor, a MISFET is prevented from having deteriorated controllability which will otherwise occur when a tungsten film, which configures a gate electrode of the MISFET, has a tensile stress. A gate electrode of a MISFET having an AlGN/GaN heterojunction is formed from a tungsten film having grains with a relatively small grain size and having no tensile stress. The grain size of the grains of the tungsten film is smaller than that of the grains of a barrier metal film configuring the gate electrode and formed below the tungsten film.

Semiconductor device and method of manufacturing same

The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

Semiconductor device and a method for manufacturing a semiconductor device

A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.

Method of manufacturing semiconductor device with a multi-layered gate dielectric

The semiconductor device includes: a channel layer, a barrier layer, a first insulating film, and a second insulating film, each of which is formed above a substrate; a trench that penetrates the second insulating film, the first insulating film, and the barrier layer to reach the middle of the channel layer; and a gate electrode arranged in the trench and over the second insulating film via a gate insulating film. The bandgap of the second insulating film is smaller than that of the first insulating film, and the bandgap of the second insulating film is smaller than that of the gate insulating film GI. Accordingly, a charge (electron) can be accumulated in the second (upper) insulating film, thereby allowing the electric field strength at a corner of the trench to be improved. As a result, a channel is fully formed even at a corner of the trench, thereby allowing an ON-resistance to be reduced and an ON-current to be increased.

Nitride semiconductor device using insulating films having different bandgaps to enhance performance

Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.

Semiconductor memory device

To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.

Semiconductor device with varying thickness of insulating film between electrode and gate electrode and method of manufacturing semiconductor device

Foreign metal inspection equipment is provided with: a conveying device for conveying a sample to be subjected to inspection; electrodes positioned so as to face the surface of the sample; a measurement device for measuring the capacitance between the electrodes and the sample being conveyed by the conveying device; and a processing unit that inspects for foreign metal mixed in the sample on the basis of the change in capacitance measured by the measurement device.

Inspection equipment and inspection method

Growing community of inventors

Tokyo, Japan

Hiroshi Kawaguchi