Toshiba Memory Corporation

Hiroshi Katougi

Satoshi Kaburaki

Katsuya Ohno

According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to manage a first cache which stores a part of a logical-to-physical address translation table in the nonvolatile memory. The first cache includes cache lines each including sub-lines. Each of entries of a first cache tag includes bitmap flags corresponding to the sub-lines in the corresponding cache line. Each bitmap flag indicates whether data of the logical-to-physical address translation table is already transferred to a corresponding sub-line. The controller determines a cache line including the smallest number of sub-lines to which data of the logical-to-physical address translation table is already transferred, as a cache line to be replaced.

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Isehara, Japan

Hiroshi Katougi