Fuji Electric Co., Ltd.

Hiroshi Kanno

Masaharu Yamaji

Hitoshi Sumida

Akihiro Jonishi

A method of manufacturing a semiconductor integrated circuit includes a first ion implantation process implanting impurity ions of a second conductivity type into a bottom surface of a semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a first current suppression layer, and a second ion implantation process implanting impurity ions of a first conductivity type into the bottom surface of the semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a second current suppression layer. The semiconductor integrated circuit includes a first well region of the first conductivity type and a second well region of the second conductivity type provided in an upper portion of the first well region. The first current suppression layer is separated from the first well region and the second current suppression layer is provided under the first current suppression layer.

Method of manufacturing semiconductor integrated circuit

A semiconductor integrated circuit includes: a first well region of a first conductivity type; a second well region of a second conductivity type provided in an upper portion of the first well region; a first current suppression layer of a second conductivity type being provided to be separated from the first well region in a lower portion of a base-body of the second conductivity type directly under the first well region and having an impurity concentration higher than that of the base-body; and a second current suppression layer of the first conductivity type provided under the first current suppression layer so as to be exposed from a bottom surface of the base-body.

Semiconductor integrated circuit

A semiconductor integrated circuit includes a semiconductor layer of a first conductivity type which is stacked on a support substrate with an insulating layer interposed between the semiconductor layer and the support substrate, a first well region of a second conductivity type buried in an upper part of the semiconductor layer so as to be separated from the insulating layer, a second well region of the first conductivity type buried in an upper part of the first well region, and an isolation region of the first conductivity type buried in the upper part of the semiconductor layer such that the isolation region surrounds the first well region and is separated from the first well region and the insulating layer.

A semiconductor integrated circuit includes a semiconductor substrate of a first conductivity type, a first well region of a second conductivity type formed in an upper portion of the semiconductor substrate, a second well region of the first conductivity type formed in an upper portion of the first well region, an insulating layer formed separated from the first well region on a bottom portion of the semiconductor substrate that is directly beneath the first well region, and a rear surface electrode layer formed on a bottom of the insulating layer.

Semiconductor integrated circuit and semiconductor module

A semiconductor integrated circuit includes a first well region of a first conductivity type; a second well region of a second conductivity type provided in an upper part of the first well region; a current suppression layer of the first conductivity type provided in a lower part of the semiconductor substrate immediately below the first well region, separated from the first well region; and an isolation region of the second conductivity type provided in an upper part of the semiconductor substrate, separated from the first well region, a reference potential being applied to the isolation region. The semiconductor substrate is the second conductivity type.

A semiconductor device that has a level shift circuit, an anterior stage circuit, and a posterior stage circuit. The level shift circuit transmits an input signal from a primary potential system to a secondary potential system different from the primary potential system. The anterior stage circuit including a first transistor receives a gate driving signal delivered by the level shift circuit. The posterior stage circuit including a second transistor with the same channel type as that of the first transistor drives a switching element according to the output signal from the first transistor. The threshold voltage of the first transistor is set at a lower value than the threshold voltage of the second transistor.

Semiconductor device and power converter equipment

A semiconductor device is provided with a first well region of a first conduction type having a first voltage (voltage VB) applied thereto, a second well region of a second conduction type formed in the surface layer section of the first well region and having a second voltage (voltage VS) different from the first voltage applied thereto, and a charge extracting region of the first conduction type formed in the surface layer section of the second well region and having the first voltage applied thereto. This inhibits the operation of a parasitic bipolar transistor.

Semiconductor device

In a high-side region, a first n-diffusion region, in which a PMOS constituting a gate drive circuit is formed, and a second n-diffusion region, in which a p-diffusion region is formed, are provided on a surface layer of a psubstrate. An NMOS constituting a gate drive circuit is formed in the p-diffusion region. A p-type isolation diffusion region at ground potential is provided between the first n-diffusion region and the second n-diffusion region, and the first re-diffusion region and the second n-diffusion region are electrically isolated. The first n-diffusion region is connected to a VB terminal at a power source potential. The second n-diffusion region is connected to a terminal at a reference or floating potential. The p-diffusion region is connected to a VS terminal at a reference potential. Accordingly, it is possible to suppress parasitic operation due to a surge, without using external components, and without element breakdown.

Growing community of inventors

Matsumoto, Japan

Hiroshi Kanno