Sanyo Electric Co., Ltd.

Hiroshi Kaneko

Takahiko Masumoto

Kazuhiro Kimura

Takashi Uchino

Yutaka Hirakoso

Syugo Yamashita

Shigeaki Hayashibe

Yoshihiko Kon

Volume adjustment is performed in small steps at a DSP () and volume adjustment is performed in wide steps at electronic volume circuits (L,R). Adjustment only by the DSP () is performed for a small volume range less than or equal to a predetermined level. For a volume higher than or equal to the predetermined level, fine adjustment by the DSP () at the transient period of volume adjustment is combined to reduce the increment of variation so that the volume adjustment is performed gradually.

Level adjustment circuit

A receiver receives FM multiplex broadcast data of both RDS and DARC systems by using one front end. A BIC detection circuit ( ) detects a block identification code (BIC) included in received data. A coincidence/non-coincidence detection circuit ( ) judges whether or not a BIC detection timing is correct and emits a coincidence/non-coincidence pulse. A forward protection circuit ( ) counts a frequency of outputs of non-coincidence pulses and retains an established synchronous condition until the counted value exceeds a predetermined value. Then, a forward protection control circuit ( ) inhibits the forward protection circuit from performing a count operation while a search is performed for selecting a station. Also, a rearward protection circuit ( ) counts a frequency of outputs of coincidence pulses and establishes a synchronous condition when the counted value reaches a predetermined value. Further, a rearward protection control circuit ( ) inhibits the rearward protection circuit from performing a count operation while a search is performed.

Synchronous circuit for FM multiple broadcast receiver

Received signals are digitized by a comparator, and sampled by regenerated clock signals synchronized to a carrier. Biphase symbol data are demodulated based on the sampling data. A biphase decoder circuit performs subtraction of the biphase symbol data to be paired. The subtraction result is compared with threshold values by data judgment circuitry which then judges inversion of the biphase signals to be paired. An RDS-ID detector circuit detects inversion of RDS signals by detection of either continuity or a ratio of signals received for a certain length period. Alternatively, RDS signals are detected by stability of output from the pair judgment circuit to detect a combination of biphase symbols.

RDS signal detection device

An RDS signal is binarized by a comparator (2) and the output is sampled by a regeneration clock in synchronism with a regeneration carrier to provide sampled data. Then, by means of an accumulator (an adder 6 and a D-FF7) or a low pass filter (12), an integration result of the sampled output is obtained for each biphase symbol and by means of a biphase decoder circuit (9), the integration results are subjected to a subtraction between two symbols making up a pair. A differentially coded RDS data can be obtained using the sign of the subtraction result, which is differentially decoded in a differential decoder circuit (11) to provide an RDS data. In addition, the absolute value of the subtraction result is compared with a predetermined threshold value to provide reliability data for each differentially coded RDS data using the comparison result. The lower one of the consecutive reliability data may be assumed to be the reliability data for the RDS data.

Data demodulator device

A receiver is provided capable of receiving both RDS (Radio Data System) and DARC (DAta Radio Channel) system FM multiplex broadcasting. An RDS signal demodulating circuit is provided with a PLL circuit which comprising a first frequency divider for dividing an output of a crystal oscillator, a phase comparator for inputting an output of the first frequency divider, a low-pass filter connected with the phase comparator, a VCO connected with the low-pass filter, and a second frequency divider for dividing an output of the VOC and outputting the divided output signal to the phase comparator. An output of the VCO is transmitted as a reference clock RDSCL for demodulation of an RDS signal.

FM multiplex broadcasting receiver for receiving RDS and DARC signals

A demodulating circuit demodulates a received signal, and outputs patterns of demodulated data and reliability information bits indicating correctness of the demodulated data. These are supplied to first and second shift registers (4 and 5), respectively. When the number of reliability information bits of Level 1 in the second shift register is a predetermined value or less, a shift operation is repeated a plurality of times. When a reliability information bit of Level 1 is outputted, an error correction control circuit (7) successively outputs all possible bit patterns of the demodulated data An EXOR gate (10) generates all possible patterns of demodulated data An error correcting circuit (11) carries out error correction for all the patterns. When the number is larger than the predetermined value, the error correction is carried out only for the demodulated data supplied from the demodulating circuit in a conventional manner.

Error correction device

An offset circuit (2) detects an offset word serving as a synchronization pattern. By being triggered by the detection, main and subordinate synchronization detection circuits (5 and 6) detect the periodicity of the offset word only during a predetermined backward guard period. Both synchronization detection circuits (5 and 6) detect offset words at different timings. Therefore, if one synchronization detection circuit (5 or 6) fails in detection of synchronization, it is possible to use a detection result of the other synchronization detection circuit (5 or 6). Moreover, received data during the backward guard period is stored in a data memory (11). Therefore, it is possible to use the stored data as received data after detection of synchronization. Even after establishment of synchronization, the synchronization detection circuit (5 or 6) continuously detects the periodicity of an offset word at a timing different from an established timing. Therefore, when established synchronization is incorrect, it can immediately be corrected.

Synchronization regeneration circuit

A digital modulating signal, which is a binary conversion of an RDS signal by a comparator, is sampled by a D-FF with a regeneration clock synchronized with a carrier regenerated by a carrier regeneration circuit. Next, a comparator output is input by an edge detection circuit where a data edge is detected, and the edge interval between this edge and the sampling timing edge of the regeneration clock is detected by a reliability judgment circuit where the edge interval is encoded and output as reliability data. Then, the reliability data is added as LSB data to various sampling data, and data for various symbols is regenerated at the data regeneration circuit. This minimizes the influence of the error data on the data regeneration circuit even if data is sampled erroneously.

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Gunma-ken, Japan

Hiroshi Kaneko