Renesas Electronics Corporation

Hiroshi Kamizuma

Taizo Yamawaki

Yukinori Akamine

Koji Maeda

Satoshi Tanaka

Sungwoo Cha

The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state.

Semiconductor integrated circuit and circuit operation method

The transmitter of the transceiver includes: a transmitter-side mixers of a transmitter-side modulator; a transmitter-side voltage-controlled oscillator; and a transmitter-side divider. The divider having a dividing factor of a non-integral number is supplied with an oscillating output of the oscillator. A pair of non-quadrature local signals having a phase difference of 90&#xb0; plus a predetermined offset angle is produced by the divider and supplied to the mixers. The transmitter includes a phase-shift unit which converts a pair of quadrature transmit signals having a phase difference of about 90&#xb0; on an analog basis into a pair of non-quadrature shifted transmit signals. Consequently, quadrature modulation is performed by the mixers. Use of a similar configuration enables the reduction in interference of an RF signal with local signals supplied to receiver-side mixers of the receiver.

Transceiver

A transceiver includes an oscillator and a plurality of communication blocks. Each of the communication blocks includes frequency dividers and mixers. Frequency dividing number of the frequency divider included in one communication block is set to an even-numbered integer, and transmission local signals supplied from the frequency dividers to the mixer become quadrature signals having a phase difference of 90 degrees. The frequency dividing number of another frequency divider in the another communication block is set to a non-integer, and communication local signals supplied from the frequency divider to the mixers become non-quadrature signals having a phase difference at a predetermined offset angle from 90 degrees. The transceiver further includes a converting unit for giving a compensation offset amount having almost the same absolute value and having a polarity opposite to that of the offset angle to communication analog signals related to the mixer of the another communication block.

A transceiver includes an oscillator and a plurality of communication blocks. Each of the communication blocks includes frequency dividers and mixers. Frequency dividing number of the frequency divider included in one communication block is set to an even-numbered integer, and transmission local signals supplied from the frequency dividers to the mixer become quadrature signals having a phase difference of 90 degrees. The frequency dividing number of another frequency divider in the another communication block is set to a non-integer, and communication local signals supplied from the frequency divider to the mixers become non-quadrature signals having a phase difference at a predetermined offset angle from 90 degrees. The transceiver further includes a converting unit for giving a compensation offset amount having almost the same absolute value and having a polarity opposite to that of the offset angle to communication analog signals related to the mixer of the another communication block. Increase in the number of voltage-controlled oscillators for multiband communication, broadening of the band, and increase in phase noise can be reduced.

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Kokubunji, Japan

Hiroshi Kamizuma