Hitachi, Ltd.

Fujifilm Healthcare Corporation

Hiroshi Kakita

Yutaka Uematsu

Satoru Watanabe

Takayuki Ono

Hideki Osaka

Hitoshi Ueno

Akio Idei

Masabumi Shibata

Satoshi Muraoka

Yuichi Fukuda

Michinori Naito

Takashi Miyagawa

Taishi Sumikura

Yuusuke Fukumura

Yoshihiro Kondo

Kazunori Nakajima

Shinta Takano

Nobuo Yagi

Kazuhiro Amino

Yusuke Fukumura

Dzikowski Jens Uwe

A plurality of transmission and reception circuits are connected to a plurality of vibration elements. The transmission and reception circuit includes a basic delay circuit and a fine delay circuit. The basic delay circuit delays a transmission signal and a reception signal for sub beamforming. The fine delay circuit is configured to be capable of performing delay finer than that of the basic delay circuit. A quantized delay error is compensated for by the fine delay circuit at the time of transmission.

Ultrasonic diagnostic device and ultrasonic probe

A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.

Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein

In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.

DRAM having SDRAM interface and flash memory consolidated memory module

When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.

DRAM with SDRAM interface, and hybrid flash memory module

An information processing apparatus includes a data ownership table which is a list of processor numbers having data on each of lines in a level 2 cache. When data at an address pointed by a store instruction exists in the level 2 cache, the apparatus references the table to selectively issue an invalidation request only to a processor in which data at the address exists, but does not issue the request to a processor in which the data does not exist. The path busy ratio can be reduced and the data coherency among processors and a system controller can be maintained with a small amount of logics. When a system controller is divided into a plurality of interleaves operating independently of one another and respectively issuing an invalidation request, the requests issued from the interleaves are put into a queue, and requests having different destination processor numbers are simultaneously issued.

Information processing apparatus with cache coherency

Growing community of inventors

Tokyo, Japan

Hiroshi Kakita