Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Socionext Inc.

Matsushita Electrical Industrial Co., Ltd.

Matsushita Electric Industrial

Hiroshi Kadota

Tokuzo Kiyohara

Hideshi Nishida

Kozo Kimura

Tetsuya Tanaka

Nobuo Higaki

Kunihiko Hayashi

Kazuya Furukawa

Tadashi Okamoto

Kazushi Kurata

Shigeki Fujii

Toshio Sugimura

Yoshiteru Mino

Ichiro Okabayashi

Katsuyuki Kaneko

Masaitsu Nakajima

Jiro Miyake

Hiroyuki Morishita

Akira Miyoshi

Eisuke Ichinohe

Satoshi Takashima

Atsushi Ito

Yoshinori Maeda

A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot.

Processor and program execution method capable of efficient program execution

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.

Data processor and program for processing a data matrix

A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

Circuit group control system

A bus for data transmission, bus switches for slicing the bus, and four arithmetic blocks are provided to perform a series of fixed-point arithmetic operations. Each of the four arithmetic blocks has a plurality of digit-serial arithmetic units, namely a multiplier, an adder/subtracter, and a shifter. Each of the digit-serial arithmetic units has the functions of receiving a plurality of input digits representative of an input operand and a digit position indicator of each of the input digits and providing a plurality of result digits representative of an arithmetic result of the input operand and a digit position indicator of each of the result digits to any other one of the plurality of digit-serial arithmetic units. Particularly, the digit-serial adder/subtracter contains therein a selector for input switching so that the digit-serial adder/subtracter can perform butterfly arithmetic.

Reconfigurable digit-serial arithmetic system having a plurality of digit-serial arithmetic units

Five processing units, namely one data memory, three arithmetic units, and one data memory, are connected together in a cascade arrangement so as to form a single arithmetic pipeline. Likewise, five control devices are connected together in a cascade arrangement and a control signal requesting that a series of data processing operations should start is sent to the first stage control device. Each control device starts to send a micro instruction to a corresponding processing unit upon detection of a processing start request bit in the received control signal and sends a signal which lags the control signal by a delay time equal to a number of cycles required to complete a processing operation of the processing unit, to the next stage control device. The first stage control device is provided with a loop counter operable to count the number of times processing is repeated and automatically generates a processing start request and a processing end request to the next stage control device.

Cascaded arithmetic pipeline data processor

A data processor of the invention includes plural memories, plural arithmetic units, a data transfer unit and a network. The data transfer unit transfers various data to predetermined memories, and switches the connections between the memories and the arithmetic units by using the network. The control unit adds a processability judgement signal to a data read from a predetermined memory in reading the data, so as to make a pair of the data and the processability judgement signal. Each of the arithmetic units receives the data and the processability judgement signal, conducts predetermined processing on the received data, delays the received processability judgement signal by the number of cycles equal to its own processing cycle, and outputs resultant data obtained through the processing and the delayed processability judgement signal. Accordingly, in storing ultimate resultant data in a predetermined storage unit, the storage unit stores the ultimate resultant data as effective data on the basis of the processability judgement signal added to the resultant data. The data processor attains wide application and can be applied to various types of multimedia applications by switching the connections between the memories and the arithmetic units by using the network.

Data processor

An image processing apparatus which performs a process which enhances incongruous pixel values in an original image, including an object pixel selecting unit for selecting an object pixel out of pixels which compose the original image, a plurality n of filter units, each of which extracts pixel values of a set of pixels, including the selected object pixel, on one of a predetermined surface and a predetermined line which pass through the object pixel, out of pixels in a predetermined range, wherein each predetermined surface and predetermined line is at a different inclination, a relative size comparing unit for comparing pixels values of each set of pixels extracted by each filter unit and specifying a filter unit whose pixel values best approximate to a predetermined standard, and a first pixel value enhancing unit for enhancing a pixel value of the object pixel based on only the pixel values of the specified filter unit.

Image processing apparatus and image processing method for favorably

A data transfer apparatus for providing efficient data transfer between one memory device and multiple devices by providing high speed switching of the multiple devices according to a count of the number of the data transfers performed between the one memory device and any of the multiple devices. The data transfer apparatus comprises a transferring unit for controlling a data transfer between the memory and a device; a counting unit for counting one each time data is transferred; and a selecting unit for selecting a device in accordance with a count value by decoding the count value output from the counting unit. The transferring unit controls the data transfer between the memory and the device selected by the selecting unit. The above data transfer apparatus may include the counting unit consisting of n-bits of a binary counter, 2.sup.n devices, and the selecting unit consisting of a decoder that inputs n-bits and outputs 2.sup.n -bits of data.

Data transfer apparatus and system providing high speed switching to

A calculator calculates projection coordinates of principal vertexes of a displayed object with respect to a projection plane from a visual point. An evaluation device evaluates whether surfaces of the object which are determined by the principal vertexes are visible or invisible from the visual point. A result of the evaluating by the evaluation device is indicated. A memory stores information of a position of a predetermined virtual operation plane. A pointing device is movable on an actual operation plane. A calculator connected to the memory and the pointing device calculates a correspondence point on the virtual operation plane which corresponds to a position of the pointing device when the pointing device moves on the actual operation plane. A calculator calculates a half line which starts from the correspondence point and which intersects with the virtual operation plane at a predetermined angle. A setting device sets the predetermined angle. A calculator calculates a point of an intersection between the half line and the displayed object. A calculator calculates projection coordinates of at least part of the half line with respect to the projection plane. The calculated projection coordinates of at least part of the half line are indicated.

Apparatus with two dimensional screen on which three dimensional objects

A method of data transfer applicable to processing elements which are interconnected by a network to form a multiprocessor system, whereby when a datum is to be transferred from a processing element to the network, the datum is sent to a transfer controller of the processing element at the same time that it is being read out from memory to be used by the processor of the processing element, or as it is being generated from the processor and written into memory. Thus, the system performance can be substantially improved, since the time required to execute each data transfer can be 'hidden' within the processor execution time.

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Toyonaka, Japan

Hiroshi Kadota