Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Other

Tosbac Computer System Company Limited

Tokyo Shibaura Electric Co., Ltd.

Toshiba Microelectronics Corporation

Toshiba Micro-computer Engineering Corp.

Hiroshi Iwahashi

Masamichi Asano

Hiroto Nakai

Yuuichi Tatsumi

Hidenobu Minagawa

Hideo Kato

Isao Sato

Mizuho Imai

Akira Narita

Shigeru Kumagai

Fujio Masuoka

Shinichi Kikuchi

Kazuhisa Kanazawa

Riichiro Shirota

Ryouhei Kirisawa

Satoshi Inoue

Ryozo Nakayama

Tetsuo Endoh

Kiyofumi Ochii

Kazuto Suzuki

Masaki Momodomi

Shoji Ariizumi

Sadayuki Yokoyama

Masazi Mito

Yoshihisa Iwata

Kiyoshi Kobayashi

Tadayuki Taura

Yasuo Itoh

Sumio Tanaka

Kazuhiro Ogawa

Kazunori Ohuchi

Seigo Suzuki

Shigeyoshi Watanabe

Hiroyuki Hirata

Kazunori Kanebako

Kaoru Nakagawa

Hiroaki Kishi

Ichiro Kobayashi

Shinji Koga

Shuji Yamamoto

Masahiko Chiba

Kouji Michiba

Nobuaki Hiraga

Toshiyuki Fujimoto

Naoshige Kubo

Shinichi Maekawa

Yuichi Kawasaki

Kuniyoshi Yoskikawa

Yutaka Chida

Masami Asano

Taketo Yamakawa

Hidefumi Yamanaka

Toshinobu Nishibata

Kazutoshi Nishimoto

In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the thresheld voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of '0' or '1' of the binary data are stored such in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

Non-volatile semiconductor memory device and data programming method

In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of '0' or '1' of the binary data are stored such in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the date latch circuits can be formed at any positions remote from the memory cell array.

In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of &ldquo;0&rdquo; or &ldquo;1&rdquo; of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of &ldquo;0&rdquo; or &ldquo;1&rdquo; of the binary data are stored such in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

On a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of &ldquo;0&rdquo; or &ldquo;1&rdquo; of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

Non-volatile semiconductor memory device with programming voltage generating system and data programming method

The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

Memory cell of nonvolatile semiconductor memory device

A row line selection circuit comprises first and second decoding sections and NMOS transistors. The first decoding section receives a first address signal and generates first selection signals. The second decoding section receives a second address signal and generates second selection signals. The NMOS transistors each of which has a gate for receiving one of the first selection signals, one end of a current path of each of the NMOS transistors being connected to receive the one of the second selection signals. The NMOS transistors classified into groups, each group including a predetermined number of the transistors which are prepared in correspondence with row lines lying adjacent to each other. One of the first selection signals is supplied to the predetermined number of NMOS transistors in one of the groups, and one of the second selection signals is supplied to one of the predetermined number of NMOS transistors in each group.

Welded structure made of low thermal expansion coefficient alloy and welding material therefore

A nonvolatile semiconductor memory includes a memory cell string containing a selection transistor and at least one cell transistor which is connected to the selection transistor and has a floating gate. Cell transistors are arranged in a memory cell array. The transistors each have a charge accumulation layer. A potential supply circuit supplies a potential different from a ground potential to gates of the cell transistor at least read operation and when the memory cell array is unselected.

Nonvolatile semiconductor memory

A virtual grounded type EEPROM including a memory cell array includes a plurality of memory cells arranged in a matrix. A control gates of the memory cells of the same row are connected to one of word lines. The adjacent two memory cells of the same row are connected such that a drain of one of them is connected to a source of the other. The source and drain of the adjacent two memory cells are connected to one of bit lines. A row decoder selects one of the word lines and a column decoder selects one of the bit lines. A program circuit applies a high voltage to the drain of a selected memory cell. The row decoder determines whether a high voltage should be applied to the selected word line. The row decoder also determines whether or not to permit the charge storage layer to store charges. The data programming is executed such that data programming for the memory cells of one column is completed first and then data programming for the memory cells of an adjacent column is started, and such that data programming makes progress from the memory cells at one end of each memory cell array to the memory cells at the other end of the memory cell array.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory is disclosed. This nonvolatile semiconductor memory includes a memory cell string containing a selection transistor and at least one cell transistor which is connected to the selection transistor and has a floating gate. This memory further includes a bias circuit for, when the selection transistor is unselected, supplying a potential different from the ground potential to the gate of the cell transistor connected to the unselected selection transistor.

Growing community of inventors

Yokohama, Japan

Hiroshi Iwahashi