Ricoh Company, Ltd.

Tokyo Institute of Technology

Hitachi, Ltd.

Fujitsu Corporation

Fujitsu Microelectronics Limited

Softbank Corporation

Hiroshi Ishihara

Tetsuro Tamura

Hiromasa Hoko

Kazuhiro Takahashi

Keiichi Suzuki

Kenji Maruyama

Makoto Ohkura

Yoshihisa Fujisaki

Nobuyoshi Natsuaki

Masanobu Miyao

Naoki Yamada

Masao Tamura

Yoshihiro Arimoto

Masaomi Yamaguchi

Takashi Tokuyama

Naotsugu Yoshihiro

Michihiko Tsuda

Yasuo Nara

Koji Aizawa

Satoshi Hasegawa

Eisuke Tokumitsu

Yoshiaki Tabuchi

In the mobile communications of the fifth generation or the like, a radio relay apparatus capable of stably over a wide area realize a three-dimensional network, in which a propagation delay is low, a simultaneous connection with a large number of terminal apparatuses in a wide-range and high-speed communication can be performed, and a system capacity per unit area is large, in radio communications with terminal apparatuses including devices for the IoT, and there is no influence on radio wave frequency resources, is provided. The radio relay apparatus comprises a floating object provided with a radio relay station and controlled to be located in a floating airspace with an altitude less than or equal to 100 [km] by an autonomous control or an external control, an optical communication section for performing optical communication with an optical communication destination via an optical antenna apparatus controllable to change outgoing directional beam, an information acquisition section for acquiring at least one of optical-beam control information provided with a radio relay station and a reception sensitivity of the optical communication section, and a beam control section for controlling a directional beam of the optical antenna apparatus based on information acquired by the information acquisition section.

3D-compatible directional optical antenna

An information processing apparatus includes a receiving unit configured to receive a utilization request for one of plural services provided by a computer; a service attribute information storage unit configured to store service attribute information of each of the services, the service attribute information including information indicating a type of the service and information indicating an evaluation of a content of the service; and a service recommending unit configured to search the service attribute information storage unit for the service attribute information corresponding to the type of the requested service, and determine a utilization-recommended service based on the evaluation information in the service attribute information retrieved from the service attribute information storage unit.

Information processing apparatus, information processing method, and image forming apparatus

The invention relates to a semiconductor element used for a nonvolatile semiconductor storage device or the like, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof and a manufacturing method of those, and has an object to provide a semiconductor element in which scaling and integration of cells are possible, storage characteristics of data are excellent, and reduction in power consumption is possible, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof, and a manufacturing method of those. A pn junction diode GD with a ferroelectric gate as the semiconductor element includes a gate electrode formed on a ferroelectric film, an inversion layer formation region in which an inversion layer is formed in a semiconductor substrate below the ferroelectric film according to a polarization direction of the ferroelectric film, a cathode region formed on one of both sides of the inversion layer formation region, and an anode region formed on the other of both the sides.

Semiconductor element, semiconductor storage device using the same, data writing method thereof, data reading method thereof, and manufacturing method of those

A ferroelectric memory device includes a gate electrode formed on a semiconductor body via a ferroelectric film, first and second diffusion regions being formed in the semiconductor body at respective sides of a channel region, wherein the ferroelectric film comprises a first region located in the vicinity of the first diffusion region, a second region located in the vicinity of the second diffusion region, and a third region located between the first and second regions, wherein the first, second and third regions carry respective, mutually independent polarizations.

Ferroelectric memory, multivalent data recording method and multivalent data reading method

A drawing instruction processor refers to a bit map line table that shows whether the bit arrays in the row unit are the same in the order of concentrations. The drawing instruction processor decides whether dither patterns to be used for the adjacent specified drawing ranges are the same, by referring to the BLT, and links the drawing ranges to which the same pattern can be applied. Based on this, the drawing processor carries out a batch writing using a dither pattern prepared in advance into the specified range in the page memory. The dither pattern to be used for the drawing is prepared by linking a plurality of the same basic patterns to have a length corresponding to the length of the word length. As a result of such an arrangement, it is possible to achieve a high-speed processing.

Image processing apparatus, drawing processing method, and computer program

An image processing apparatus includes an overlay detector and a memory. The image processing apparatus and method sequentially process graphic rendering instructions for image data. The graphic rendering instructions include first and second graphic rendering instructions. The first graphic rendering instruction is input immediately preceding said second graphic rendering instruction. The first graphic rendering instruction contains first rendering data representing a first original image to render a first output image. The second graphic rendering instruction contains second rendering data representing a second original image to render a second output image. The first original image is overlaid by the second original image.

Apparatus and method for image processing capable of accelerating image overlay process

A semiconductor apparatus is provided that is thermally stable in a post process and is suitable for fabricating a gate insulator having a laminated structure with various high permittivity oxides, and a process is provided for producing the same. In order to achieve a high function formation of a gate insulator, a silicon nitride film having a specific inductive capacity approximately twice as much as that of silicon oxide, and which is thermally stable, is not provided with a Si&#x2014;H bond and is used as at least a portion of the gate insulator. Further, an effective thickness of a gate insulator forming a multilayered structure insulator laminated with a metal oxide having a high dielectric constant, in conversion to silicon oxide, can be thinned to less than 3 nm while restraining leakage current.

Semiconductor device and process for producing the same

An image processing method converts line vectors of an input graphic path and an input clip path into run sets in dot coordinates passed by the line vectors, and generates a region run describing a closed region represented by the entire path from the run sets, so as to obtain a graphic region run and a clip region run, and extracts an overlapping portion of the graphic region run and the clip region run to generate a plot region run. The scan line conversion and the clipping form a rasterizing process.

Image processing method, image processing apparatus, image output apparatus and storage medium

The invention is directed to a writing method to effectively suppress inter-cell interference when writing data to a single transistor type ferroelectric memory. When V is a writing voltage, stripe-like conducting electrodes are row electrodes, and semiconductor stripes are column electrodes, then the writing method includes a first procedure and a successive second procedure based on V/3 rule. In the first procedure, when a voltage of +V is applied to the row electrode of the cell being observed, while a voltage of zero is applied to the column electrode, and voltages of +V/3 are applied to the other row electrodes, and voltages of +(2/3)V are applied to the other column electrodes, then in the second procedure, a voltage of zero is applied to the row electrode of the cell being observed, while a voltage of +V/3 is applied to the column electrode, and voltages of +V/3 are applied to the other row electrodes, and voltages of zero are applied to the other column electrodes. In the first procedure, when a voltage of -V is applied to the row electrode of the cell being observed, while a voltage of zero is applied to the column electrode, and voltages of -V/3 are applied to the other row electrodes, and voltages of -(2/3)/V are applied to the other column electrodes, then in the second procedure, a voltage of zero is applied to the row electrode of the cell being observed, while a voltage of -V/3 is applied to the column electrode, and voltages of -V/3 are applied to the other row electrodes, and voltages of zero are applied to the other column electrodes.

Method of writing data to a single transistor type ferroelectric memory

The present invention relates to a product-sum operation circuit element and a circuit for addition by weighting a number of signals input in one neuron circuit in a neural network, and can provide an adaptive-learning neuron circuit for changing an interval of output pulses by learning by connecting a simple pulse generating circuit consisting of capacitance, resistance, unijunction transistor and the like. A product-sum operation circuit element according to the present invention, includes an insulator substrate, a single crystal semiconductor thin film having a p-n-p or n-p-n structure in a lateral direction formed in the shape of stripes on the insulator substrate, a ferroelectric thin film deposited thereon for covering at least the semiconductor stripe structure, and a stripe-like electrode consisting of a metal or a polycrystalline semiconductor further formed thereon for intersecting the semiconductor stripes at a right angle or suitable angle.

Ferrelectric adaptive-learning type product-sum operation circuit

An amorphous or polycrystalline film which continuously covers the exposed surface of a single crystal substrate and an insulating film, is deposited in ultra-high vacuum and then heat-treated. The film is subjected to solid phase epitaxial growth at a temperature far lower than in prior-art methods, whereby a single crystal film is formed.

Growing community of inventors

Tokyo, Japan

Hiroshi Ishihara