Renesas Electronics Corporation

Hiroshi Ise

Shinichi Uchida

Yoshitsugu Kawashima

A semiconductor wafer having a plurality of interconnect layers, includes a plurality of chip-composing portions, a dicing region separating the chip-composing portions from each other, and a plurality of inter-chip interconnects formed in the dicing region and electrically connecting adjacent ones of the chip-composing portions, wherein each of the inter-chip interconnects has a width of an intermediate portion narrower than widths of connection end portions connected to the adjacent ones of the chip-composing portions.

Method for manufacturing semiconductor device, semiconductor chip, and semiconductor wafer

A method for manufacturing a semiconductor device includes forming a semiconductor wafer including a plurality of interconnect layers, the semiconductor wafer including: a plurality of chip-composing portions; a dicing region separating the chip-composing portions from each other; and a plurality of inter-chip interconnects formed in the dicing region and electrically connecting adjacent ones of the chip-composing portions; and forming semiconductor chips by dicing the dicing region so as to divide the chip-composing portions, wherein each of the inter-chip interconnects has a width of an intermediate portion narrower than widths of connection end portions connected to the adjacent ones of the chip-composing portions.

A method for manufacturing a semiconductor device includes forming a semiconductor wafer including a plurality of interconnect layers, the semiconductor wafer including: a plurality of chip-composing portions; a dicing region separating the chip-composing portions from each other; and a plurality of inter-chip interconnects electrically connecting adjacent ones of the chip-composing portions and formed in one of the interconnect layers and in the dicing region; a dummy metal pattern comprising a plurality of dummy metals, the dummy metal pattern being formed in at least one of the interconnect layers over or below the inter-chip interconnects only in an area corresponded to a region where the inter-chip interconnects are arranged and corresponded to a region therearound; and forming semiconductor chips by dicing the dicing region so as to divide the chip-composing portions.

Growing community of inventors

Kanagawa, Japan

Hiroshi Ise