Matsushita Electric Industrial Co., Ltd.

Hiroshi Imanishi

Eiji Miyagoshi

Hiroshi Takeno

Toshiyuki Araki

Masaki Toyokura

Toshihide Akiyama

Shintarou Nakatani

A processor, a task management table, and a scheduler are built in a microcontroller. The processor sequentially runs a plurality of tasks for controlling hardware engines (cores) respectively allocated thereto. The task management table stores task management information which includes state information (ST INFO) representative of the execution state of each task, priority information (PRI INFO) representative of the execution priority of each task, and core identification information (CID INFO) representative of the allocation of the tasks to the cores. The scheduler allows the processor to switch between tasks on the basis of the task management information when a given instruction is decoded or when the execution of any one of the cores is terminated.

Microcontroller, data processing system and task switching control method

The present invention makes it possible to achieve restoration of decoding processing more intricately in comparison with commonly-used techniques. The present invention increases post-restoration data reliability and is applicable to real-time decoding processing. A variable length code converter of the present invention provides an abnormal code detection signal when a bit-string subjected to conversion corresponds to none of variable length codes that belong in predetermined coding systems. At this time, a controller provides an error signal, and according to the error signal a bit-string is continuously output from a memory which stores bit-strings to be decoded. When the controller detects a header indicative of data partition from an output bit-string of the memory, it cancels the error signal. As a result, bit-string decoding resumes after the detected header.

Code converter, variable length code decoder, and associated methods

A variable-length-code decoder of this invention decodes an input bit stream including an input bit string having a codeword of a fixed-length code and a plurality of codewords of variable-length codes combined in a predetermined format. The decoder includes: a shifter for shifting the input bit string by a desired number of bits; a pattern detector for detecting a specific pattern in the bit string, and outputting a detection signal; two code tables provided for the respective variable-length codes, each code table having the length of each codeword (codeword length) and the decoded-word corresponding to the codeword, and outputting a codeword length and a decoded-word of a corresponding codeword based on the bit string output from the shifter; a processor for storing the format of the input bit string, outputting the length of the fixed-length code and decoded data of the fixed-length code, and selecting, for each of the variable-length codewords, one of the code tables to which the variable-length codeword belongs, based on the detection signal and the format; a codelength selector for selecting the codeword length or the fixed-length code, and for setting the shift amount for the input bit string in the shifter; and an output circuit for selectively outputting the decoded-word or the decoded data.

Apparatus and method for decoding variable-length code

A prefix data generating portion is arranged such that a bit string having bits in predetermined number supplied from a barrel shifter is compared, from the head part thereof, with predetermined patterns and that there is supplied a less-bit bank address assigned to the identical predetermined pattern. In a look-up table, a decoded data is addressed using (i) an upper address of the bank address and (ii) a lower address of a plurality of remaining bits of the code, other than the predetermined pattern. Accordingly, the look-up table can be addressed with an address in which the number of bits is smaller than that of the code. This reduces the look-up table in capacity, enabling to provide a variable-length decoding apparatus reduced in hardware size.

Variable-length decoding apparatus

A code sequence includes a header code consisting of a series n 0 bits terminated by a 1 bit. A shifter outputs the code sequence in bit strings. Each bit string is made up of plural bits. A priority encoder performs arithmetic operation to count the number of consecutive 0 bits from the most significant bit of each bit string. An accumulator adds the results found by the priority encoder. A comparator compares the sum found by the accumulator with a set value n. The comparator outputs a coincidence signal if these two values are found equal. The priority encoder outputs a 1-bit-inclusion indication signal if a bit string includes a 1 bit. Upon receipt of the coincidence signal and the 1-bit-inclusion indication signal, a first AND circuit outputs a header detection signal. As a result of such arrangement, the code sequence is processed in units of plural bits, whereupon high-speed header code detection is accomplished without requiring the shifter and the accumulator, both of which are components of a header detector, to operate at high speed.

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Osaka, Japan

Hiroshi Imanishi