Hitachi, Ltd.

Hiroshi Ikegaya

Hidenori Umeno

Tsuyoshi Watanabe

Takashige Kubo

Yoshio Ukai

Nobuyoshi Sugama

An absolute address translated from a logical address input by a user program by an address translation circuit and a prefix translation circuit, is compared with contents of a virtual processor prefix register. On the basis of the comparison result, a multi-processor field of a translation lookaside buffer (TLB) has a value indicating whether or not the entry corresponds to an area common among virtual processors. The MP field of the TLB is compared with contents of the multi-processor register, and a virtual processor field of the TLB is compared with contents of a virtual processor register. If the value coincides with the multi-processor field or if the value does not coincide with the multi-processor field and the value coincides with the virtual processor field, contents of an absolute address field of the TLB are input to an absolute address register. This increases the effective capacity and utilization of the TLB to avoid decreasing of performance of the virtual machines.

Apparatus and method for translating logical addresses for virtual

In order to carry out address translation which can reduce an overhead of the VMCP to support a virtual storage, a flag indicating a common segment in the virtual machine and a system identifier are held in a TLB, and a VM identifier is held in a segment table origin stack. For the common segment, a current VM identifier is compared with the VM identifier in the segment table origin stack to determine validity of a TLB entry, and for a non-common segment, a system identifier read from the segment table origin stack is compared with the system identifier in the TLB entry to determine validity of the TLB entry.

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Sagamihara, Japan

Hiroshi Ikegaya