Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Hitachi Haramachi Electronics Co., Ltd.

Hiroshi Ichige

Toshio Okochi

Junichi Kono

Shoji Sasaki

Ryoichi Kobayashi

Shigeo Kuboki

Norio Moriyama

Yoshiaki Ajima

Takamasa Fujinaga

Satoko Iwama

Isao Saitoh

Yoshinori Atsuwata

Yoshiaki Homitsu

An electric power steering drive system provided with a motor with its torque pulsation reduced, and a controller characterized by excellent manufacturability. The stator core of a motor is composed of an annular back core and a plurality of teeth created separately from the back core and secured on the inner periphery of the back core. An 8-pole/9-slot, 10-pole/9-slot or 10-pole/12-slot relationship is found between the number of the magnets of a rotor (number of poles) and the number of slots. The diameter of the stator coil is 1.0 mm or more. A motor controller comprises a power module, a conductor module and a control module. The terminal of the power module and the bus bar of the conductor module are connected by welding, whereas the terminal of the power module and terminal of the control module are connected by soldering.

Controller for electric power steering and electric power steering system

The communication control device allows a plurality of data items to be transferred to and from external devices, such as a CPU and a memory, via an external bus having a different data bus width in DMA (direct memory access) transfer mode. DMA transfer is controlled by the DMA controller provided in the communication control device. The DMA controller produces a signal indicating that a plurality of data items are continual.

Communication control device and a communication system using the same

The number of bits of data items read in parallel fashion and the number of bits of data items written in parallel fashion are related to be at least a whole number multiple of 2, thereby to achieve enhancement in the efficiency of data transfer between a semiconductor memory device and the exterior thereof. Further, in a semiconductor memory device of FIFO type, the number of stored data items is calculated using the values of a write counter and a read counter, thereby to achieve the accurate acquisition of the number of stored data items even when the operations of reading and writing data items coincide. In a semiconductor memory device having a built-in address counter, the value of the address counter or an external address signal is selected on the basis of an external instruction in order to address a memory cell, thereby to achieve facilitation of random accesses to memory cells and also the clearing of the data items of any desired memory cells.

First-in first-out semiconductor memory device

Growing community of inventors

Kodaira, Japan

Hiroshi Ichige