Fujitsu Corporation

Socionext Inc.

Fujitsu Semiconductor Limited

Hiroshi Hatano

Yi Ge

Koichi Suzuki

Noboru Kobayashi

Masahiko Toichi

Kazuo Horio

Takashi Nishikawa

Yasuhiro Oyama

A data processing apparatus includes a computing unit that performs a matrix computation between data streams whose unit data is of a matrix format; a determining unit that for each matrix obtained by the matrix computation by the computing unit, determines based on the value of each element included in the matrix, an exponent value for expressing each element included in the matrix as a floating decimal point value; a converting unit that converts the value of each element into a significand value of the element, according to the exponent value determined by the determining unit; and an output unit that correlates and outputs the exponent value and each matrix after conversion in which the value of each element in the matrix has been converted by the converting unit.

Advanced computational processes and methods of using the same

A vector processor includes an instruction fetching unit configured to acquire an instruction, a decoding/issuing unit configured to decode the instruction and issuing the instruction, an operation group configured to include a plurality of operation units and a register configured to store the element data column, wherein the plurality of operation units include a first operation unit processes a first type instruction and a second operation unit processes a second type instruction and the first type instruction; and when a plurality of divided instructions, for which the element data of an instruction to be issued has been divided, are processed by the second operation unit, in a case where the second type instruction is not present, the decoding/issuing unit issues the divided instructions, and in a case where the second type instruction is present, the decoding/issuing unit issues the instruction to be issued without performing division.

Vector processor and vector processor processing method

A matrix calculation unit may include a matrix operation unit and a converting unit. The matrix operation unit may include functions to perform a matrix operation of a first size with respect to data stored in a memory, and to perform a matrix operation of a second size with respect to the data stored in the memory, where the second size is enlarged from the first size. The converting unit may convert in at least one direction in the memory between a data array suited for the matrix operation of the first size and a data array suited for the matrix operation of the second size.

Matrix calculation unit

A memory controller includes: a first generating unit that generates a read-address to read a data element sequence having a plurality of data elements from a bank of a memory; a second generating unit that generates a position signal indicating a position of a data element to be selected from the data element sequence, and an order signal indicating a storing order for storing the data element to be selected into a register; and a selector unit that selects, according to the position signal, the data element to be selected from the data element sequence read out from each of the plurality of the banks, and stores the selected data element in the storing order indicated by the order signal into the register, wherein the data element stored in the register is processed in the storing order by a vector processor.

Growing community of inventors

Kawasaki, Japan

Hiroshi Hatano