Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Nippon Electric Co., Ltd.

Nec Corporation

Sanyo Chemical Industries, Ltd.

Hiroshi Gokan

Kohji Hashimoto

Katsuya Nakamoto

Mitsuhiro Kitta

Masayoshi Suzuki

Junya Tanaka

Ryuichi Ishii

Yoshitake Ohnishi

Kunikazu Koura

Sotaro Esho

Kenji Ogawa

Hiroshi Ando

Yuki Iwagami

Hisanao Tsuge

Nobukazu Takeuchi

Naruki Suetake

Masaru Fuku

Katsuya Tsujimoto

Masaki Itoh

Shigeki Yamakawa

Keita Yamaguchi

Kenji Mizuno

Hidehiko Matsuya

Kazuhide Saigo

Hajime Iida

Kazuki Arata

Shougo Tatsumi

Akio Ohtsuji

Masahito Mukainaru

Yasushi Saotome

This semiconductor device includes a first dummy terminal extending from a second conductor toward one side in a first direction, a second dummy terminal extending from a fourth conductor toward another side in the first direction, and a third dummy terminal extending from a third conductor through between a third conductive plate and a fourth conductive plate toward one side in a second direction, and connected to a second AC terminal. In a state in which ends of the first dummy terminal, the second dummy terminal, first control terminals, second control terminals, second AC terminals, first AC terminals, N terminals, and P terminals are exposed, the first conductive plate, a second conductive plate, the third conductive plate, the fourth conductive plate, first switching elements, second switching elements, a first conductor, the second conductor, the third conductor, and the fourth conductor are sealed by a resin member.

Semiconductor device and manufacturing method therefor

Two semiconductor elements and a capacitive element are located at vertices of a triangle. A first shortest path between the semiconductor elements, and a second shortest path and a third shortest path between the capacitive element and the two respective semiconductor elements, satisfy (first shortest path)&#x2265;(second shortest path) and ((first shortest path)+(second shortest path))&#x2265;(third shortest path). A first electrically conductive metal pattern and a second electrically conductive metal pattern each have a thickness that is equal to or larger than two times a depth of a skin through which current flows owing to skin effect generated according to frequency characteristics of current paths having: a first resonance frequency obtained from capacitances and inductances between the semiconductor elements; a second resonance frequency between one of the semiconductor elements and the capacitive element; and a third resonance frequency between another one of the semiconductor elements and the capacitive element.

Power module

Provided is a gate drive circuit and a gate drive system, with which current unevenness among power devices connected in parallel can be reduced more. A gate drive circuit includes: an objective waveform generation unit configured to generate an objective waveform; a drive waveform generation unit configured to generate a drive waveform from the objective waveform, by referring to on-timing set information and off-timing set information; a drive control unit configured to drive the power device to turn the power device on/off, based on the drive waveform; a state detection unit configured to detect the state of the power device; a predicted waveform generation unit configured to generate a predicted waveform of a voltage; and an update unit configured to update the on-timing set information and the off-timing set information, based on the result of the state detection and the result of comparison to the predicted waveform.

Gate drive circuit and gate drive system

In an electric power steering device assisted by a brushless motor, an induced voltage from a brushless motor is detected when a main power supply is off. The motor is determined to be in a high rpm state when the induced voltage is in a first transient state from a voltage&#x2264;a high rpm detection threshold Th1 to a voltage&#x2265;Th1, thereby setting an intermittent excitation cycle of a revolution angle sensor connected to the motor to a short cycle. The motor is determined to be in a low rpm state when the induced voltage becomes a voltage&#x2265;a high rpm detection threshold Th2 after a wait period corresponding to an electrical angle between peaks or valleys of an output voltage has elapsed in a second transient state from a voltage&#x2265;Th1 to a voltage&#x2264;Th2, thereby setting the cycle to a long cycle.

Electric power steering device

A synchronization detection PLL section generates an ON synchronized signal formed as a result of synchronization control based on a diode ON synthesized signal. The synchronization detection PLL section also generates an OFF synchronized signal formed as a result of synchronization control based on a diode OFF synthesized signal. A stator gate instruction generator PWM section generates a gate instruction signal for controlling the switching of a switching element on the basis of the ON synchronized signal and the OFF synchronized signal.

Power converter

A microcomputer that exercises driving control and power-generation control over a motor generator unit and a power-generation maintaining unit that, separately from the power-generation control exercised by the microcomputer, maintains a power-generation process performed by the motor generator unit are provided. While the microcomputer is operating normally, the power-generation maintaining unit allows the microcomputer to exercise the power-generation control. When an abnormality has occurred in the microcomputer, the power-generation maintaining unit acts as a backup or secondary controller to maintain the power-generation process performed by the motor generator unit, in an autonomous manner independently of the microcomputer.

Secondary control system for maintaining motor generator power generation during primary control failure

To miniaturize and standardize an on-vehicle electronic controller by improving an input filter circuit in the device. Direct input interface circuits and a direct output interface circuit are connected to a data bus of a microprocessor, which has a nonvolatile memory for storing a control program and so on and a RAM memory for computing. ON/OFF signals inputted from indirect input interface circuits are transmitted to the RAM memory via a variable filter circuit, in which a filter constant is set by a constant setting register, and interactive serial communication circuits. A filter constant stored in the nonvolatile memory is stored in the constant setting register via the interactive serial communication circuits.

On-vehicle electronic controller

A vehicle-mounted communication control apparatus includes: microprocessor to which serial-parallel converter for master station is connected; and common control circuit to which serial-parallel converter for substation is serial-connected to serial-parallel converter . The control apparatus includes first storage device for storing transmission from master station to substation; distribution storage device for transferring command data to device memory when command data stored in first storage device is write/setting command; reply packet generation device for generating up-reply information to microprocessor ; second storage device for reading out on the principle of preceding input or preceding output while storing in order reply information and evacuating the delay; and reply packet composing device for adding latest information to reply information and sending back resultant reply information.

Vehicle-mounted electronic control apparatus

In a vehicle built-in electronic control apparatus, second control programs are written, second RAM memory for calculation processing and second input/output ports, and a serial-parallel converter for full duplex two-way serial communication for mutually conducting data communications between the main CPU and the sub CPU in operation of the controlled vehicle, and at the time of starting operation of the controlled vehicle, a part of the control constants stored in the first nonvolatile memory is transferred to the second RAM memory through the serial-parallel converter for the serial communication and the sub CPU performs predetermined calculation based on the contents of the second control programs of the second nonvolatile memory and the contents of the control constants transferred to the second RAM memory.

Vehicle built-in electronic control apparatus

A cmmunications control system for elevators having control units including at least respective car control units and elevator hall registration control units, each of the control units having a node, the nodes being connected to each other via a network, and each of the nodes having a management table establishing correspondence between node number and network address. The elevator communications control system includes a node acting as a master when a first network address corresponding to the node number of this node is, upon referring to the management table, a specific address in the management table, and sending to all other nodes a broadcast communication to notify that the node is a temporary master having the first network address added and receives from another temporary master a broadcast communication for notifying that this other node is the temporary master having a second network address corresponding to the node number of the other temporary master added, if the first network address and the second network address conform to specific conditions.

Elevator communication controller and communication control method

A communications control system for elevators in which synchronization instructions do not result in all units bearing data receiving loads, and smooth data transfer may be realized. A node acting as a master sends synchronization start data to one slave from among many slaves; receives synchronization completion data from the slave, and sends subsequent synchronization start data to a subsequent slave, in order; and adjusts the timing for sending synchronization start data sending so that it matches a target cycle, assuming that an interval for sending the synchronization start data is a synchronization start data sending cycle, based on: amount of time from the sending of the synchronization start data until the receiving of the synchronization completion data; an amount of time required for sending the data, being calculable from the number of sending data stored in a sending buffer until the time of sending; and a target time for the synchronization start data sending cycle.

Communications control system for elevators

A data interface for communicating data between processors having: a writing-side register group in which data in a writing-side processor which transmits data is written in response to a clock signal; a reading-side register group into which the data written into the writing-side register group is transferred and written in response to a later clock operation, the data being read out by a reading-side processor of a data receiving side; a write controller for selectively writing data in a register in the writing-side register group in accordance with an address signal and a write signal of the writing-side processor; and a read controller for selectively reading data from a register in the reading-side register group in accordance with an address signal of the reading-side processor; so that a double buffer structure consisting of the writing-side buffers and the reading-side buffers causes the address signal and the data signal to individually be connected in the writing side and the reading side. Thus, the respective processors are able to transfer data without mutual interference.

Data interface and high-speed communication system using the same

A method for the geometry independent planarization of dielectric films on integrated circuits is disclosed. The method comprises forming the dielectric film, forming a polymer layer which polymer has the viscosity of 5,000 cps or less at 200.degree. C., reducing the viscosity of the polymer under baking to create a planar surface, hardening the polymer by the radiation or the electric beam and etching said polymer layer to transfer the planar surface to said dielectric film.

Planarization of dielectric films on integrated circuits

Disclosed is a novel novolak resin comprising structural units having a trimethylsilyl group. A resist material highly resistive to dry etching is obtained by adding a photosensitive diazo compound to this novolak resin. The resist material is useful in various lithography methods to form a positive resist pattern. This resist material is used in a pattern forming method of a two-layer type, in which a fine pattern is formed in a thin film of the resist material by lithography and then transferred into an underlying thick organic polymer layer by dry etching of the underlying layer with the resist pattern as mask. Curing of the resist pattern by irradiation with deep UV rays is effective for further improvement in the precision of the transferred pattern.

Growing community of inventors

Tokyo, Japan

Hiroshi Gokan