Kabushiki Kaisha Toshiba

Hiroshi Gojohbori

Takeo Maeda

Yoshitaka Tsunashima

Hidetoshi Koike

Kazunari Ishimaru

Fumitomo Matsuoka

Takeo Nakayama

A first trench is formed in an element-separating region on the surface of a semiconductor substrate, and a second trench is formed in an alignment mark region thereof. When a first insulating substance is deposited on the substrate surface so as to bury the first and second trenches, a first insulating film is formed into a recessed shape in both the first and second trenches. A second insulating substance having an etching rate slower than that of the first insulating substance is formed on the first insulating film, and further etched to leave the second insulating film only over the second trench. The overall thickness of the device is reduced in such a way that the upper surface of the first insulating film in the first trench becomes flush with the semiconductor substrate surface. A part of the surface of the insulating substance on the alignment mark portion projects so as to be usable as an alignment mark. Alternatively, when a first trench is formed extending to both the element-separating and alignment mark regions and further when an insulating film is deposited on the substrate surface so as to bury both the first and second trenches, a first projecting insulating film can be formed between the two trenches. A second insulating film whose etching rate is slower than that of the first insulating film is formed on the projecting insulating film and further etched to leave the second insulating film so as to cover only the first projecting insulating film. The overall thickness is reduced in such a way that the upper surface of the first insulating film becomes flush with the semiconductor substrate surface, and further the remaining second insulating film is removed. The remaining first insulating film is usable as an alignment mark portion.

Method of making a semiconductor device with alignment marks

A semiconductor device comprises a semiconductor substrate having a major surface, a trench device isolation region having a trench selectively formed to define at least one island region in the major surface of the semiconductor substrate and a filler insulatively formed within the trench, an elongated gate electrode insulatively formed over a central portion of the island region so that each of its both ends which are opposed to each other in the direction of its length overlaps the trench device isolation region, and source and drain regions formed within the island region on the both sides of the gate electrode. The surface of the trench device isolation region is formed lower than the major surface of the semiconductor substrate. Those portions of the major surface of the semiconductor substrate that are located under the gate electrode at the boundary with the trench device isolation region are rounded, and the radius of curvature of these portions of the major surface of the semiconductor substrate is selected to be not less than 50 nm.

Method of manufacturing a trench isolation having round corners

A semiconductor integrated circuit device having a bipolar transistor and contact in the form of a wired layer by using different impurities for doping the emitter electrode and the wired layer of the device, both of which are made of polysilicon. The emitter electrode, formed on an emitter region of a p-type silicon semiconductor substrate, is doped with an n-type impurity having a low diffusion coefficient. A polysilicon wired layer, formed on an impurity diffusion region in an active region of the semiconductor substrate, is doped with another impurity that can effectively destroy native oxide films. With such an arrangement of selectively using impurities, the temperature of thermally treating the emitter region can be less than 850.degree. C.

Semiconductor integrated circuit device and method of manufacturing the

A semiconductor device of this invention includes an N-type semiconductor region functioning as a collector of a bipolar transistor, a silicon dioxide film doped with boron and formed in contact with the surface of the N-type semiconductor region, a P-type semiconductor region formed in contact with the silicon dioxide film doped with boron in the N-type semiconductor region and functioning as a base of the bipolar transistor, and an N-type semiconductor region formed in the P-type semiconductor region and functioning as an emitter of the bipolar transistor.

Semiconductor device including bipolar transistor having shallowed base

In a semiconductor device, an emitter electrode has a polysilicon layer provided in a first contact hole and on a first insulating film. The polysilicon layer is in contact with an emitter region and is covered with a metal layer. A second contact hole is provided on a part of a second insulating film located on a substantially flat portion of the metal layer. A third contact hole is provided in those portions of the first insulating film and a second insulating layer which are located on a base region.

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Yokohama, Japan

Hiroshi Gojohbori