Hitachi, Ltd.

Renesas Technology Corp.

Hiroshi Fukiage

Isao Shimizu

Masayuki Sato

Masayuki Satou

A test circuit is provided on a probe card or a wafer on which semiconductor chips to be tested are formed. The test circuit and each of the semiconductor chips to be tested are electrically connected to each other to perform testing, whereby the test can be carried out without using a tester. Conducting a test in such a wafer stage within an aging device allows the simplification or omission of a test subsequent to packaging.

Test system and manufacturing of semiconductor device

A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determinating the read data and outputting the result of determination is provided over a semiconductor chip equipped with a memory.

Semiconductor integrated circuit and method of checking memory

A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determining the read data and outputting the result of determination is provided over a semiconductor chip equipped with a memory

Growing community of inventors

Kodaira, Japan

Hiroshi Fukiage