Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Hiroshi Benno

Hiroyuki Tsujikawa

Kenji Shimazaki

Masatoshi Sawada

Mitsumi Itoh

Junko Honma

Yoshiyuki Saito

Eiji Takahashi

Shirou Yoshioka

Yukihiro Fukumoto

Takashi Yoneda

Koji Tamura

Tsutomu Kamiyoshi

Tsuneo Uenishi

Disclosed is a dicing system including a protection layer forming apparatus, a patterning apparatus, a plasma treatment apparatus, a measuring apparatus that obtains at least of first processing data relating to a protection layer, second processing data relating to a mask, and third processing data relating to element chips, and a control unit that operates at least one of the protection layer forming apparatus, the patterning apparatus, and the plasma treatment apparatus on a recipe that is defined for each of the apparatuses. The control unit determines, based on at least one of the first processing data, whether or not to modify the recipe, the second processing data, and the third processing data, modifies the at least one of the recipes if the recipe needs to be modified, and operates at least one of the protection layer forming apparatus, the patterning apparatus, and the plasma treatment apparatus based on the modified recipe.

Dicing system and dicing method

It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.

Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device, and apparatus for generating pattern for semiconductor device

Semiconductor device method of generating semiconductor device pattern method of semiconductor device and pattern generator for semiconductor device

A method of evaluating noise immunity of a semiconductor device is provided. An actual circuit including the semiconductor device is represented by an equivalent circuit which has a target equivalent circuit, a noise source equivalent circuit, and an external equivalent circuit connected in parallel. The target equivalent circuit represents the semiconductor device. The noise source equivalent circuit represents a noise source outside the semiconductor device, and supplies noise to the target equivalent circuit. The external equivalent circuit represents a circuit outside the semiconductor device. The noise immunity is evaluated based on a voltage or current which arises in the target equivalent circuit by the noise. In this way, the immunity of the semiconductor device against extraneous noise can be evaluated in consideration of the effects of the circuitry outside the semiconductor device.

Method, apparatus, and computer program for evaluating noise immunity of a semiconductor device

A backup memory, a DMA (direct memory access) controller, and a WDT (watch dog timer) are provided in addition to a CPU (central processing unit), a RAM (random access memory), and a peripheral circuit. The DMA controller exercises control so that respective data of the CPU, RAM and peripheral circuit is saved in the backup memory each time the CPU, being under normal operation, supplies a counter reset signal to the WDT, and so that the data that has been saved in the backup memory is restored to the CPU, the RAM and the peripheral circuit, respectively, if the WDT has detected a program runaway and outputted a time-over signal. Therefore, even in a case where a program runaway has occurred in the CPU, normal operation is permitted to be resumed from midway in the program.

Semiconductor integrated circuit having improving program recovery capabilities

Growing community of inventors

Osaka, Japan

Hiroshi Benno