Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Hiroshi Azakami

Takaaki Konishi

Kazuya Ueda

Naoya Tokunaga

Hisaya Kato

Yoshikazu Hayashi

Noriaki Omoto

Takashi Hasegawa

Hiroaki Ozeki

Ippei Kanno

Haruka Takano

Kazuaki Suzuki

Masahiro Hamada

Shougo Sasaki

Yousuke Kimura

Misao Teshima

Tap coefficients of an FIR filter are prevented from converging to wrong values. A waveform equalizer for performing waveform equalization of an input signal and outputting a waveform equalization result as an output signal includes: an FIR filter for performing a convolution operation between the input signal and a plurality of tap coefficients; an IIR filter for performing a convolution operation between the output signal and a plurality of tap coefficients; an adding section for adding an operation result of the FIR filter and an operation result of the IIR filter and outputting an addition result as the output signal; an error detecting section for detecting an error of the output signal; and a tap coefficient updating section for updating respective tap coefficients of the FIR filter and the IIR filter based on the error. The tap coefficient updating section sets a step size for updating the tap coefficients of the FIR filter to a value smaller than a step size for updating the tap coefficients of the IIR filter during a period from start of operation of the waveform equalizer until a predetermined condition is satisfied.

Waveform equalizer

In a high-frequency signal level detection apparatus for detecting an inputted signal level of a high-frequency signal, an AGC circuit executes an AGC on an intermediate frequency (IF) signal obtained by converting a frequency of a received high-frequency signal, using an RFAGC value and an IFAGC value for controlling gains of the high-frequency signal and the IF signal, respectively, based on the IF signal so that an output level of the IF signal is substantially constant. A controller previously measures first and second relational data, indicating an RFAGC value and an IFAGC value relative to the inputted signal level of the received high-frequency signal, respectively, measures the RFAGC and IFAGC values when a high-frequency signal to be measured is received, and detects the inputted signal level of the received high-frequency signal using the measured first and second relational data based on the measured RFAGC and IFAGC values.

High-frequency signal level detection apparatus and high-frequency signal receiver apparatus using the same

In a digital broadcast receiving apparatus for amplifying a received modulated digital signal wave with automatically adjusted gain and demodulating the modulated signal wave to a digital signal, a tuner frequency-converts the modulated digital signal wave to generate a first modulated signal. A first automatic gain control amplification unit controls gain of the tuner to make a level of the first modulated signal at a first predetermined level. An A/D converter converts the first modulated signal into a second modulated signal. A demodulator demodulates the second modulated signal to generate a first demodulated digital signal. A second automatic gain control amplifier generates a second demodulated digital signal where frequency fluctuations included in the digital modulated wave are eliminated.

Digital broadcast receiving apparatus

An input signal DT contains a segment synchronization signal compliant with the ATSC standard. A clock multiplication sectionmultiplies a clock CK. A switchable sampling sectionselects a sample point from among a plurality of timing points that are defined by the multiplied clock, and samples the input signal DT at the selected sample point. Moreover, the switchable sampling sectionswitches sample points from one to another in a synchronization-unestablished state. Once the segment synchronization is established, a synchronization detection device may maintain a synchronization-established state until the field synchronization detection fails, or the synchronization detection device may output a synchronization detection signal after shifting it in the time direction based on a bit error rate RT of the input signal.

Synchronization detection apparatus

A digital demodulation apparatus automatically controls gain based on a state of receiving a digital modulated signal. The digital demodulation apparatus amplifies a digital modulated signal wave received through the air with the gain automatically controlled so as to have a predetermined amplitude. In the digital demodulation apparatus, a receive level variation detector detects receive level variation, an amount of noise components of the received digital signal wave. A gain controllercontrols the gain with a receive level variation adaptive control signal based on the detected receive level variation, the amount of noise components.

Automatic gain control for digital demodulation apparatus

In an automatic gain control amplifier, an RF automatic gain controller controls the gain of a radio frequency signal. A frequency converter frequency-converts the radio frequency signal into an intermediate frequency signal. An IF automatic gain controller controls the gain of the intermediate frequency. A level detector detects a signal level of the gain-controlled intermediate frequency signal, and generates a level signal. An automatic gain control signal generator separately controls, based the level signal, the RF automatic gain controller and the IF automatic gain controller.

Automatic gain control apparatus

In a clock recovery circuit for DTV using a VSB modulation method, if the frequency of the symbol clock is fs, since the frequency difference between the fs/2 component signal of the VSB signal and the pilot signal is constant at fs/2, it is possible accurately to detect the phase error from their differential signal. Furthermore there is no distortion of the clock signal frequency of the VSB signal, even when the symbol data is distorted by multi-pass distortion or the like, since clock signal regeneration is performed by frequency domain processing. By employing this type of principle and performing phase error detection for each symbol at a time, it is possible to ensure a high speed tracking performance for clock signal regeneration.

Clock recovery circuit

VSB receiver

A method and device determines the metric value threshold used in a Viterbi synchronization evaluation circuit which enables to synchronize with a correct coding rate when multiple coding rates exist in the input signal to a Viterbi decoder. A first coding rate setting unit sets a coding rate for which the metric value threshold may need to be identified, and a second coding rate setting unit sets a coding rate other than the coding rate set by the first coding rate setting unit. A metric value threshold setting unit decreases values gradually from the maximum metric value threshold as the synchronous/asynchronous state of the Viterbi decoder is monitored by a synchronous/asynchronous monitor in order to find the minimum metric value threshold where the Viterbi decoder is not completely synchronized limit for judging asynchronicity). This minimum value is determined as the metric value threshold for the coding rate set by the first coding rate setting unit.

Method and device for determining thresholds of metric values used in

A digital broadcast receiver for receiving a digital modulation signal of the present invention includes channel selection means inputting a digital modulation signal of a radio frequency band and frequency converting a desired digital modulation signal into a designated intermediate frequency signal; oscillation means for generating a local oscillation signal used for frequency conversion at the channel selection means; oscillation frequency control means for controlling a frequency of the local oscillation signal at the oscillation means; phase noise characteristic control means for improving a phase noise characteristic of the local oscillation signal generated at the oscillation means; filter means for extracting the intermediate frequency signal selected at channel selection means; orthogonal detection means for orthogonally detecting the intermediate frequency signal extracted at the filter means; A/D converter means for converting the analog output of the orthogonal detection means into a digital signal; and digital demodulation means for digitally demodulating the output of the A/D converter means; and makes a high performance digital reception possible which can improve an AFC function by the channel selection means and can improve a bit error rate at the same time.

Digital broadcast receiver

A receiving apparatus is presented, in which a channel frequency can be selected over a wide band with an increased attenuation at an image frequency and/or at a local oscillation frequency by including a tunable filter having a following construction. Microstrip lines are connected between either one of the input or the output terminal or both of the input and output terminals of the tunable filter; a plurality of resonant circuits are formed by each of a plurality of coils and a plurality of variable capacitance diodes; and the coils are electromagnetically coupled and where a voltage applied to each cathode of each of a plurality of variable capacitance diodes through each of a plurality of resistors is controlled to tune a frequency to be received.

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Ibaraki, Japan

Hiroshi Azakami