Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Hiroshi Arimoto

Shigehiko Sasa

Takeshi Kamata

Makoto Okada

Koichi Hashimoto

Naoki Yokoyama

Satoru Asai

Shunichi Muto

Teruyoshi Yao

Morimi Osawa

Akira Endoh

Makoto Kosugi

Seiichiro Yamaguchi

A simulation instructing unit instructs a simulation unit, which generates signal characteristics, to generate the signal characteristics. A characteristic value extracting unit extracts, from the signal characteristics, characteristic values for distinguishing between a signal characteristic generated by setting a first simulation parameter and a signal characteristic generated by a second simulation parameter. A simulation parameter determining unit determines a first mapping relationship from the characteristic values to the simulation parameters with the characteristic values obtained by setting a plurality of set values in the simulation parameters and with the set values.

Computer aided design apparatus, computer aided design program, computer aided design method for a semiconductor device and method of manufacturing a semiconductor circuit based on characteristic value and simulation parameter

An integrated circuit manufacturing method comprising: calculating a threshold value from a value of a parameter which characterizes at least a part of a design pattern shape of a transistor on the target path; calculating a difference between the calculated threshold value and a target threshold value; calculating a change quantity of a gate length corresponding to the difference between the threshold value and the target threshold value according to the functional relation between the threshold value of the transistor and the gate length, which is determined based on the empirical value or the experimental value; reducing, by the change quantity, the gate length of the transistor on the target path; and manufacturing an integrated circuit on the basis of design information of the circuit including the transistor of which the gate length is changed.

Integrated circuit manufacturing method, design method and program

A computer converts dimensions of design patterns of components of the transistors configuring the semiconductor circuit or component parameters extracted from in-design physical characteristics of the transistors into simulation parameters inputted to the simulator, organize the plurality of transistors included in the semiconductor circuit into a plurality of groups, selects any selection groups from the plurality of groups, sets fixed parameter values as component parameters of the non-selected groups other than the selection groups in the plurality of groups, sets the combinations of the component parameters in the selection groups, acquires circuit characteristics with respect to each combination of the component parameters, selects a group as a next selection group different from the selected groups, and repeatedly executing the setting the fixed parameter values through the selects a group as a next selection group different.

Semiconductor circuit design method and semiconductor circuit manufacturing method

A method of a layout a semiconductor circuit has obtaining transistor characteristic information on the basis of layout information about regions formed with transistors, obtaining a polynomial expression representing a relationship between characteristic values of a circuit including of the transistors and the transistor characteristic information, calculating a plurality of characteristic values corresponding to plural sets of transistor characteristic information by use of the polynomial expression, selecting part of the plurality of characteristic values on the basis of a restriction about the characteristic values, the layout information or the transistor characteristic information; and obtaining the transistor characteristic information or the layout information corresponding to the selected characteristic values.

Layout method of semiconductor circuit, program and design support system

The width values of transferred patterns of respective evaluation patterns transferred using a test photo mask () are calculated by first calculation unit () based on the relationship with the opening ratio of flare generation patterns. The distribution of the calculated width values of the respective transferred patterns is linearly approximated by second calculation unit () and the inclination thereof is calculated. On the basis of a table defining the inclination of the width values of the respective transferred patterns (the ratio of dimension fluctuation), the amount of correction is changed for each pattern by correction unit (). Consequently, the amount of dimension fluctuation caused by local flares can be accurately calculated. This enables accurately performing pattern-dimension corrections against local flares.

Apparatus and method for correcting pattern dimension and photo mask and test photo mask

A method of fabricating a semiconductor device includes the steps of illuminating a structure formed on a surface of a substrate by an incident optical beam incident to the structure with a predetermined incident angle with respect to the surface, measuring a polarization state of an exiting optical beam exiting from the structure in response to an illumination of the structure by the incident optical beam, and evaluating a size of the structure in a direction parallel to the surface from the polarization state of the exiting optical beam, and adjusting a parameter of production of a semiconductor device in response to the size.

Fabrication process of a semiconductor device using ellipsometry

A method for plasma treatment is disclosed which effects detection of the amount of particles in an plasma generation area measuring the electron density in the particles based on the numerical value of the electric density in the plasma generation area.

Method for plasma treatment and apparatus for plasma treatment

In a plasma equipment and a plasma treatment method of a semiconductor device capable of reducing electron shading effect and also suppressing charge damage without affecting various characteristics in plasma process, a distance between a substrate bias electrode and A counter electrode is set less than two times as long as a mean free path of electron. High frequency electric power of 100 kHz to 1 MHz is supplied to the substrate bias electrode, while high frequency electric power of 1 MHz to 100 MHz is supplied to the counter electrode.

Plasma treatment method

A quantum interference effect transistor comprising a semiconductor substrate, an n-type first semiconductor layer, a channel second semiconductor layer, an n-type third semiconductor layer, a gate electrode, a source electrode, a drain electrode, a source region and a drain region, said second semiconductor layer having an electron affinity larger than that of the first and third layers to generate a two dimensional electron gas channel, characterized in that the channel second layer between the source and drain regions consists of lead portions and a middle portion sandwiched with them, and in the middle portion the channel is divided into two channel passages without forming a separation layer in the second layer. The first, second and third layers form a quantum well structure. The middle portion of the second layer is thicker than the lead portions, so that a quantum well width at the middle portion is wider and has a larger amount of bending of a conduction band bottom Ec to divide an electron probability distribution into two parts with peaks.

Quantum interference effect semiconductor device and method of producing

A quantum box semiconductor structure in which truncated triangular, or quadrilateral, pyramid base portions are formed on the main surface of a silicon semiconductor substrate defined, selectively, by a (111) B or a (100) plane; the triangular, or quadrilateral, truncated pyramid base portions have corresponding three, or four, (111) A plane sides, respectively. Corresponding triangular, or quadrilateral, quantum boxes of a second semiconductor material having a narrower energy band gap and larger electron affinity than the first, silicon semiconductor material of the base portions are formed on the corresponding triangular, or quadrilateral, top surfaces of the base portions and each has three, or four, corresponding (111) A plane sides. The quantum box lasers are formed in a succession of process steps including epitaxial growth or, alternatively, alternate epitaxial growth and etching steps. An alternative structure includes stripe-like quantum boxes of triangular cross-section. Further, the quantum boxes may be truncated and further triangular, or quadrilateral, prisms may be formed on the corresponding top surfaces of the respective boxes. A further embodiment employs truncated base portions of triangular prism cross-section and quantum wires of triangular cross-section formed thereon. Covering, clad and electrode interconnection layers are formed on the resulting structures and the main surface of the substrate, with respective electrodes being formed on the electrode interconnection layer and the bottom main surface of the substrate.

Quantum box or quantum wire semiconductor structure and methods of

A quantum interference type semiconductor device is composed of at least one bifurcated branch conductive channel with a heterojunction in a semiconductor with a band discontinuity that produced a potential well between two semiconductor regions into which a carrier is injected and from which a carrier is drained, at least one gate electrode is arranged at the side of the one bifurcated branch conduction channel, and a kind of filter using a resonance tunneling barrier arranged before or upstream of the semiconductor region into which a carrier is injected. The filter passes a carrier having a certain energy legvel to the channel whereby the level of the carrier traveling in the channel becomes equal to realize a good quantum interference effect.

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Kawasaki, Japan

Hiroshi Arimoto