Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Other

Hitachi Ulsi Systems Co., Ltd.

Renesas Technology Corp.

Hiroshi Akasaki

Masatoshi Hasegawa

Shuichi Miyaoka

Kanji Otsuka

Yuji Yokoyama

Masahiro Katayama

Takashi Nakao

Kozaburo Kurita

Ikuo Yoshida

Akiomi Kohno

Masaya Horino

Hideaki Kamohara

Yousuke Tanaka

Kunizo Sahara

Yoshiaki Emoto

Masayuki Iketani

Koichiro Sekiguchi

Shouichi Irie

Toru Kobayashi

Tetsuya Hayashida

Takayuki Okinaga

Kenichi Tajima

A semiconductor memory device capable of improving the reliability when driving a word line and capable of reducing the access delay due to the defect relief is provided. In order to prevent the multiple selection of a sub-word line of a normal memory mat and a sub-word line of a redundant memory mat, the start of the redundant memory mat is delayed from that of the normal memory mat, and in order to compensate the start delay, the shared circuit is eliminated and the bit line length is reduced in the redundant memory mat. By doing so, the read time of the bit lines is reduced and the signal amount is increased. Consequently, the same activation timing of the sense amplifier as that of the normal memory mat can be used also in the redundant memory mat.

Semiconductor memory device

Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.

Semiconductor integrated circuit device, method of testing semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device

In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.

Semiconductor integrated circuit having programmable delays for generating timing signals with time difference being non-integral multiple of clock cycle

Semiconductor integrated circuit device

The column address strobe signal (CAS) which is changed in cycles as many as a plurality of times that of a clock signal cycle is input to the memory block (MBK to MBKn). A plurality of serial data readout from the memory cell array ( ) and parallel/serial converted by a parallel/serial converter circuit ( ) in synchronism with a clock signal cycle are output for every cycle when the column address signal (CASADR) is changed. Parallel data input to the memory block and serial/parallel converted by a serial/parallel converter circuit ( ) in synchronism with the clock signal cycle are written in the memory cell array. In this way, the access specification that the column address strobe signal is varied once per n cycles of the clock signal allows for a more rapid memory operation.

High speed clock synchronous semiconductor memory in which the column address strobe signal is varied in accordance with a clock signal

A method of manufacturing a semiconductor device wherein the back surface of a semiconductor chip is adhered closely to a substrate or a seal member through a soldering material or the like, and a metallized layer is formed on the back surface of the chip for attaining good adhesion. The metallized layer according to the present invention is a layer formed by laminating a metal silicide, a barrier metal and an oxidation preventing metal successively on the back of the chip. The layer of the metal silicide can be formed in a known heat treatment process, for example, simultaneously with the formation of bump electrodes, on a main surface of the semiconductor chip by the heat used at the time of forming such bump electrodes, or simultaneously with the mounting of the semiconductor chip by the heat used at the time of the chip mounting.

Method for forming a silicide layer and barrier layer on a semiconductor

A technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, more particularly pertains to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam, and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.

Method of bonding metals, and method and apparatus for producing

A semiconductor device of pin-grid array (PGA) type, which is adapted for surface-mounting on a printed circuit board, has lead pins arranged in a grid and standing perpendicularly on a base of the semiconductor device. In addition, a few pins are provided which are longer than said lead pins in said grid. When the device is placed on the printed circuit board for mounting, the longer pins are inserted into through-holes which are respectively formed in the printed circuit board to correspond to the position of the longer pins of the device. Thus, the tip of the lead pins are accurately positioned on the top of lands on the printed circuit board, respectively, and the lead pins do not get out of position during the mounting operation.

Pin-grid array semiconductor device

An invention relating to a technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, and more particularly pertaining to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.

Growing community of inventors

Ome, Japan

Hiroshi Akasaki