Toshiba Memory Corporation

Kioxia Corporation

Hiroo Yabe

Masayuki Usuda

Masashi Nakata

A frequency-voltage conversion circuit includes a constant current source, a first switch connected to an output of the constant current source, a first capacitor connected between the first switch and ground, a second switch connected between a first node that is between the first switch and the first capacitor, and an output node, a third switch connected between the first node and the ground, a fourth switch connected to the output of the constant current source, a second capacitor connected between the fourth switch and the ground, a fifth switch connected between a second node that is between the fourth switch and the second capacitor, and the output node, and a sixth switch connected between the second node and the ground.

Frequency-voltage conversion circuit, semiconductor device, and memory system

An oscillation circuit has a voltage generator configured to generate a linearly changing voltage, a voltage level of which linearly changes as time passes, a first comparator configured to compare the linearly changing voltage with a first reference voltage, a second comparator configured to compare the linearly changing voltage with a second reference voltage having a higher voltage level than the first reference voltage, a time-to-digital converter configured to output a bit sequence signal in accordance with a time difference between a time when the first comparator detects that the linearly changing voltage matches the first reference voltage and a time when the second comparator detects that the linearly changing voltage matches the second reference voltage, and an oscillator configured to generate an oscillation signal that oscillates at a frequency according to the bit sequence signal.

Oscillation circuit and interface circuit

A CR oscillator has a first logic inversion unit including odd-number stages of logic inversion elements connected in series, a second logic inversion unit including odd-number stages of logic inversion elements connected in series, the second logic inversion unit being connected to a latter stage of the first logic inversion unit, and two or more resistors and a capacitor connected in series between an output node of the first logic inversion unit and an output node of the second logic inversion unit. An electric potential in accordance with an electric potential of an intermediate node between the two or more resistors is supplied to an input node of the first logic inversion unit.

CR oscillator

A semiconductor circuit includes a differential amplifier having a first positive terminal, a second positive terminal, a first negative terminal, a second negative terminal, and an output terminal. The output voltage is at a level that corresponds to a voltage level obtained by subtracting a voltage of the first negative terminal and the second negative terminal from a voltage sum of the first positive terminal and the second positive terminal. A first diode has a first anode connected to one of the first positive or the first negative terminal. A second diode has a second anode connected to the other of the first negative and first positive terminal. A predetermined reference voltage is applied to the second positive terminal. And a voltage corresponding to the output voltage of the differential amplifier is fed back to the second negative terminal.

Semiconductor circuit

According to one embodiment, a skew correcting device includes a skew calculation circuit and a sampling timing correction circuit. The skew calculation circuit calculates a skew between data and a strobe signal based on sampling values obtained by sampling, at a cycle one half of or shorter than one half of a cycle of the strobe signal, the data and the strobe signal respectively based on a same clock. The sampling timing correction circuit corrects the sampling timing of the data based on the skew calculated by the skew calculation circuit.

Reception circuit

A communication device includes a timing generation circuit generates timing signals at several timing points within one period of a first clock signal. A clock sampling circuit receives the first clock signal and detects a logic level of the first clock signal at each of the timing points. A control circuit calculates a difference between the number of times a first or a second logic level is detected for the first clock signal and outputs a control signal indicating whether a duty ratio of the first clock signal is to be adjusted. A correction circuit that changes at a duty ratio of a second clock signal transmitted to the transmitting device, the duty ratio being set in accordance with the control signal. The duty ratio of the first clock signal is then adjusted by the transmitting device according to the duty ratio of the second clock signal.

Growing community of inventors

Nerima, Japan

Hiroo Yabe