Hitachi, Ltd.

Hiroo Sakaba

Kenzo Masuda

A ratioless type MIS logic circuit comprises a logic block including at least one depletion mode FET inherently having a gate-to-source parasitic capacitance and a gate-to-drain parasitic capacitance, an output capacitance, a circuit for precharging the output capacitance and depletion mode clamping FETs connected one with each of the two ends of the logic block, the clamping FETs having their gates connected with a reference potential and the threshold voltage value of the FET in the logic block being larger than those of the clamping FETs.

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Kodaira, Japan

Hiroo Sakaba