Kabushiki Kaisha Toshiba

International Business Machines Corporation

Hiroo Hayashi

Seiji Maeda

Shigeaki Iwasa

Yasuhiko Kurosawa

Mitsuo Saito

Kenta Yasufuku

Yoshiyuki Hamaoka

Kazuko Ishibashi

Hiroshi Sakai

Brian King Flachs

Brad William Michael

Nicolas Maeding

Nobuhiko Yamagami

Hiroshi Komuro

Takuya Kano

Nobuhiro Yoshida

An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.

Virtual address cache memory, processor and multiprocessor

An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.

Effective address cache memory, processor and effective address caching method

A processor includes a plurality of subfunctional units provided corresponding to respective slots of one or more pieces of operation result data including a plurality of slots for an SIMD operation; and an enable generating unit configured to, in each of the one or more pieces of the operation result data, compare a value of a predetermined slot with a value of a slot other than the predetermined slot, and disable one or more subfunctional units to which the value equal to the value of the predetermined slot is inputted, and the processor outputs the value of the predetermined slot as the value of the one or more subfunctional units which have been disabled.

Disabling redundant subfunctional units receiving same input value and outputting same output value for the disabled units in SIMD processor

A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.

Systems and methods for transferring data to maintain preferred slot positions in a bi-endian processor

Systems and methods for improving the performance of a multimedia processor system by dynamically evaluating the current performance of the system and, if necessary, updating the configurations of the individual processors to improve the performance of the system. One embodiment comprises a method implemented in a multiprocessor system, including evaluating the performance of each of a current set of configuration objects installed on the processors, selecting a preferred set of configuration objects, and replacing one or more of the configuration objects in the current set to conform the current set to the preferred set. The method may evaluate the performance of each configuration object according to user preferences and may select preferred configuration objects according to a selectable strategy that can, for example, favor unification or diversity in the types of preferred configuration objects.

Self-organized parallel processing system

Systems, methods and apparatuses for the generation of a global history are disclosed. Embodiments of the present invention may provide logic operable to generate a global history and a global history register operable to store a global history. More specifically, in one embodiment the global history logic comprises a set of multiplexers, each set corresponding to one of a set of instructions fetched in a cycle of a microprocessor, the number of multiplexers in each set equal to the number of bits of global history and each multiplexer within a set having a select signal corresponding to the same instruction to which that set of multiplexers corresponds.

Method, system and apparatus for generation of global branch history

Systems and methods for halting the execution of instructions in a microprocessor are disclosed. The halt instruction may have an operand which allows a programmer to specify which clock of a system is to be utilized in conjunction with the halt instruction. A specified number of clock cycles may then be counted using the clock identified in the instruction, after which dispatch of instructions may resume. These system and methods may also allow the execution of instructions to be halted with respect to one or more of a multiplicity of threads within a microprocessor while allowing the continued execution of instructions associated with the remaining threads.

Fine granularity halt instruction

A novel checkpoint acquisition accelerating apparatus is disclosed. When data are updated on a cache memory, a before-image acquiring section acquires the update address and the previous data and stores them in a before-image storing section. A cache flush executing section issues to a system bus a bus command requesting the contents of the updated cache block to be written-back to a main memory using all the addresses stored in the before-image storing section. A main memory restoring section, on the other hand, issues bus command requesting all the previous data stored in the before-image storing section to be updated and written in the main memory on last-in first-out basis. As a result, a checkpoint acquisition accelerating apparatus is realized which is capable of easily realizing the checkpoint and recovery function in a computer including at least a standard uniprocessor.

Checkpoint acquisition accelerating apparatus

As much tag information as corresponds to the number of blocks stored in main memories is stored in tag memories. The tag information indicates whether or not a processor belonging to a node other than the nodes containing tag memories has made an access request and the contents of a cache have been rewritten. Bus bridges perform cache coherency control, referring to the tag information. When the tag information indicates 'Modified,' the bus bridges stop the data read from the main memories and send the correct data to the requesting processor after a copy-back process of the modified block has been completed.

Growing community of inventors

Kanagawa, Japan

Hiroo Hayashi