Denso Corporation

Kabushiki Kaisha Toyota Chuo Kenkyusho

Toyota Jidosha Kabushiki Kaisha

Nippondenso Co., Ltd.

Hiroo Fuma

Norihito Tokura

Takeshi Miyajima

Kazukuni Hara

Yuichi Takeuchi

Kota Manabe

Toshio Murata

Yukio Inaguma

Naoyoshi Takamatsu

Takaji Umeno

Hideo Nakai

Nobuyuki Kitamura

Shoichi Onda

Satoshi Hirose

Yuji Nishibe

Hiromichi Kuno

Seiji Nakamura

Kazunari Moriya

Hiroyuki Kano

Takamasa Suzuki

An object is to miniaturize booster coils used in a vehicle-mounted booster converter. In the design method for a vehicle-mounted multi-phase converter including multiple booster coils and a switching circuit for generating an induced electromotive force at each booster coil by switching of current flowing to each booster coil for applying an output voltage, based on an input voltage and the induced electromotive force generated at each booster coil, to a vehicle drive circuit, a coupling factor indicating the extent by which the induced electromotive force in one of multiple booster coils contributes to the voltage between terminals of another booster coil is determined on the basis of a relationship between the coupling factor and current ripple component of each booster coil.

Vehicle-mounted multi-phase converter and design method thereof

An object is to miniaturize device size in a vehicle mounted converter. The vehicle mounted converter includes a plurality of inductors, a switching unit for switching current path, an external power acquisition unit for acquiring alternating current power from a power generation source provided separately from the mounted vehicle, and a switching means for switching a circuit connection state to a connection state of either a boost connection state for connecting one end of the inductors to a path to a battery for vehicle drive power supply and connecting the switching unit to the other end of the inductors, or a charging connection state for connecting one end of one of the plurality of inductors to the path to the battery, disconnecting one end of the remaining inductors from the path to the battery and connecting to the external power acquisition unit, and connecting the other end of the inductors to the switching unit.

Vehicle mounted converter

Provided is a driving circuit which suppresses a surge voltage at the time of switching a power semiconductor element and reduces switching loss. An element () such as an IGBT and another element () to be paired are connected, the element () is driven by a driver (), and a gate voltage is controlled by a control circuit (). When the power semiconductor element is turned off, a comparator () detects that a voltage (Vak) of the element () is a prescribed voltage, the control circuit () switches gate resistance from low resistance to high resistance to suppress the surge voltage, and the switching loss is reduced. When the power semiconductor element is turned on, start up of the voltage (Vak) is detected, and the control circuit () switches the gate resistance from high resistance to low resistance after a prescribed time to suppress the surge voltage, and the switching loss is reduced.

Driving circuit for power semiconductor element including controlling circuit that provides control when detected voltage reaches predetermined voltage

An induction machine includes a stator provided with stator windings and a first rotor provided with first rotor windings, and generates an induction current in one of the stator windings and the first rotor windings by a rotating magnetic field generated in the other of the stator windings and the first rotor windings. A synchronous machine includes a second rotor which is provided with second rotor windings connected to the first rotor windings and coupled to the first rotor, and a third rotor which is provided with permanent magnets and rotatable independent of the second rotor, and a torque acts between the second rotor and the third rotor due to the interaction between the rotating magnetic field generated in the second rotor windings and the field flux generated in the permanent magnets.

Rotating electrical machine and hybrid drive unit provided with the same

Two inverters (INV, INV) supply phase currents to three-phase coils (Y, Y). Although two phase currents must conventionally be measured and four current sensors are thus required, according to the present invention, the number of phase currents to be measured is reduced as a result of use of an observer for phase current estimation.

Motor driving control device

A n.sup.- -type source region 5 is formed on a predetermined region of the surface layer section of the p-type silicon carbide semiconductor layer 3 of a semiconductor substrate 4. A low-resistance p-type silicon carbide region 6 is formed on a predetermined region of the surface layer section in the p-type silicon carbide semiconductor layer 3. A trench 7 is formed in a predetermined region in the n.sup.+ -type source region 5, which trench 7 passes through the n.sup.+ -type source region 5 and the p-type silicon carbide semiconductor layer 3, reaching the n.sup.- -type silicon carbide semiconductor layer 2. The trench 7 has side walls 7a perpendicular to the surface of the semiconductor substrate 4 and a bottom side 7b parallel to the surface of the semiconductor substrate 4. The hexagonal region surrounded by the side walls 7a of the trench 7 is an island semiconductor region 12. A high-reliability gate insulating film 8 is obtained by forming a gate insulating layer on the side walls 7a which surround the island semiconductor region 12.

Silicon carbide semiconductor device and process for manufacturing same

A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n.sup.+ type silicon carbide semiconductor substrate 1, an n.sup.- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n.sup.+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n.sup.+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n.sup.- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n.sup.+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n.sup.- type silicon carbide semiconductor layer 2 in the side face of the trench 9. A gate electrode layer 13 is disposed through a gate insulating layer 12 within the trench 9. A source electrode layer 15 is provided on the surface of the p type silicon carbide semiconductor layer 3 and on the surface of the n.sup.+ type source region 6, and a drain electrode layer 16 is provided on the surface of the n.sup.+ type silicon carbide semiconductor substrate 1.

Silicon carbide semiconductor device with trench

A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n.sup.+ type silicon carbide semiconductor substrate 1, an n.sup.- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n.sup.+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n.sup.+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n.sup.- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n.sup.+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n.sup.- type silicon carbide semiconductor layer 2 in the side face of the trench 9.

Silicon carbide semiconductor device

A semiconductor device, which has an oxide laver with the thickness thereof being varied from portion to portion of the inner surface of a trench and can be easily produced, and a process of producing the same. An n.sup.+ type single crystal SiC substrate is formed of SiC of hexagonal system having a carbon face with a (0001) face orientation as a surface, and an n type epitaxial layer and a p type epitaxial layer are successively laminated onto the substrate. An n.sup.+ source region is provided within the p type epitaxial layer, and the trench extends through the source region and the epitaxial layer into the semiconductor substrate. The side face of the trench is almost perpendicular to the surface of the epitaxial layer with the bottom face of the trench having a plane parallel to the surface of the epitaxial layer. The thickness of a gate oxide layer, formed by thermal oxidation, on the bottom face of the trench is larger than the thickness of the gate oxide layer on the side face of the trench. A gate electrode layer is provided on the surface of the oxide layer, formed by thermal oxidation, within the trench, a source electrode layer is provided on the epitaxial layer and the source region, and a drain electrode layer is provided on the back surface of the semiconductor substrate.

Process for producing a semiconductor device having a single thermal

A semiconductor substrate 4 consisting of an n.sup.+ -type substrate 1, an n.sup.- -type silicon carbide semiconductor layer 2 and a p-type silicon carbide semiconductor layer 3, made of hexagonal crystal-based single crystal silicon carbide with the main surface having a planar orientation approximately in the (0001) carbon face. An n.sup.+ -type source region 5 is formed in the surface layer of the semiconductor layer 3, and a trench 7 runs from the main surface through the region 5 and the semiconductor layer 3 reaching to the semiconductor layer 2, and extending approximately in the �1120! direction. An n-type silicon carbide semiconductor thin-film layer 8 is provided on the region 5, the semiconductor layer 3 and the semiconductor layer 2 on the side walls of the trench 7, while a gate electrode layer 10 is formed on the inner side of a gate insulating film 9, a source electrode layer 12 is formed on the surface of the semiconductor region 5, and a drain electrode layer 13 is formed on the surface of the n.sup.+ -type substrate 1.

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Gifu, Japan

Hiroo Fuma