Kabushiki Kaisha Toshiba

Anritsu Corporation

Hironori Yoshioka

Shigeo Kouzuki

Satoshi Aida

Masaru Izumisawa

Satoshi Yanagisawa

Tatsuya Iwai

Wataru Saito

Ichiro Omura

Hitoshi Kobayashi

Hideki Okumura

Kenichi Tokano

Manabu Kimura

Masahiko Shiomi

An error rate measurement apparatus includes a display unit that displays a setting screen for setting a measurement condition of an error rate of an input signal from a DUT, and a processing unit that calculates a measurement time based on the measurement condition input to the setting screen, in which the setting screen includes a target confidence level input portion for inputting a target confidence level, a transmission rate input portion for inputting a transmission rate, a target error rate input portion for inputting a target error rate, an assumed-number-of-errors input portion for inputting an assumed number of errors during the measurement time, and a measurement time display portion for displaying the measurement time.

Error rate measurement apparatus and error rate measurement method

An error rate measurement apparatus includes a provisional confidence level calculation unit that calculates a provisional confidence level CLx by using the sum x, an upper and lower limit value update unit that substitutes the sum x for the variable min_x in a case where the provisional confidence level CLx is equal to or lower than a target confidence level CL, and substitutes the sum x for the variable max_x in a case where the provisional confidence level CLx is higher than the target confidence level CL, and a measurement time calculation unit that calculates, in a case where changes in a value of the sum x calculated by the average value calculation unit are converged in a predetermined range, a value obtained by dividing the converged sum x by a product of a data rate and a target error rate ER, as the measurement time.

The signal generation apparatus includes a phase difference calculation processing unit that calculates an initial phase difference between a division clock or an external clock selected by a clock selection unit and an initial value of the phase of the toggle pattern based on a relationship between the voltage value acquired by the phase acquisition processing unit and a change amount from the initial value of the phase of the toggle pattern, and a phase shift processing unit that moves the phase of the toggle pattern from the initial value by the initial phase difference such that a phase difference between the division clock or the external clock selected by the clock selection unit and the toggle pattern is within a predetermined range.

Signal generation apparatus and signal generation method

A signal generation device includes m transceivers, a usage amount determination unit that executes a usage amount determination process that determines the usage amount of the FIFO of each transceiver, and a phase adjustment unit that adjusts the phase of the read clock signal for the FIFO. The signal generation device performs the second usage amount determination process on the condition that the count that the usage amount of the FIFO of each transceiver is determined to be less than the usage amount threshold by the first usage amount determination process consecutively reaches the first determination count, and terminates the adjustment of the phase of the read clock signal on the condition that the count that the usage amount of the FIFO of each transceiver is determined by the second usage amount determination process to be greater than the usage amount threshold consecutively reaches the second determination count.

Signal generation device and signal generation method

A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side.

Manufacturing method of semiconductor device

A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.

Power semiconductor device including a terminal structure

A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminating portion side.

A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.

Semiconductor device and method of manufacturing the same

There is provided a power MISFET which includes a semiconductor region of a first conductivity, a semiconductor base region of a second conductivity, a pillar region, a first major electrode region of a first conductivity on the base region, a second major electrode region connected with at least the semiconductor region and a part of the pillar region, a control electrode and an electrode pad connected with the control electrode. The pillar region including a first region of a first conductivity type and a second region of a second conductivity type is not formed under the electrode pad. Also, a method for manufacturing a MISFET is provided.

Semiconductor device and its manufacturing method

A semiconductor device comprises a semiconductor element and a conductive member. The semiconductor element has a semiconductor substrate having first and second major surfaces; a semiconductor layer formed on the first major surface of the semiconductor substrate; a plurality of trenches formed on the semiconductor layer, the trenches being parallel to each other and extending to a first direction; filling material filling the trenches; a first electrode pad provided on the semiconductor layer and connected electrically to a first major electrode; a second major electrode provided on the second major surface; and a gate electrode pad provided on the semiconductor layer and connected to a gate electrode which controls conduction between the first major electrode and the second major electrode. The conductive member is connected to at least one of the first electrode pad and the gate electrode pad via a first contact area. A leading-out direction of the conductive member is substantially parallel to the first direction.

Semiconductor device

Semiconductor device and manufacturing method thereof

A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type formed on a first main surface of the semiconductor substrate, the semiconductor layer including a first region for a cell portion and a second region for a terminating portion, the second region being positioned in an outer periphery of the first region, the terminating portion maintaining breakdown voltage by extending a depletion layer to relieve an electric field; junction pairs of semiconductor layers periodically arranged so as to form a line from the first region to the second region in a first direction parallel to the first main surface in the semiconductor layer and having mutually opposite conductivity types of impurities, each of the junction pair being composed of a first impurity diffusion layer of a second conductivity type formed from a surface of the semiconductor layer toward the semiconductor substrate and a second impurity diffusion layer of a first conductivity type formed from the surface of the semiconductor layer toward the semiconductor substrate and adjacently to the first impurity diffusion layer; a base layer of a second conductivity type selectively formed on each surface layer of the junction pairs which are formed in the first region, so as to connect with the first impurity diffusion layer and the second impurity diffusion layer in the same manner; a source layer of a first conductivity type selectively formed on each surface layer of the base layers of the second conductive type; a control electrode formed above each surface of the base layers and above each surface of the source layers via an insulating film; a first main electrode formed so as to cover the control electrode and to contact the source layers and the base layers in the same manner; and a second main electrode formed on a second main surface opposite to the first main surface of the semiconductor substrate.

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Kanagawa, Japan

Hironori Yoshioka