Renesas Electronics Corporation

Nec Electronics Corporation

Lumentum Japan, Inc.

Hironori Sakamoto

Yoshihiro Nakai

Takashi Shimizu

Shunya Yamauchi

Shigenori Hayakawa

A buried semiconductor optical device comprises a semiconductor substrate; a mesa-stripe portion including a multi-quantum well layer on the semiconductor substrate; a buried layer consisting of a first portion and a second portion, the first portion covering one side of the mesa-stripe portion, the second portion covering the other side of the mesa-stripe portion, and the first portion and the second portion covering a surface of the semiconductor substrate; and an electrode configured to cause an electric current to flow through the mesa-stripe portion, the buried layer comprising, from the surface, a first, second, and third sublayer, the first and third sublayer each consisting of semi-insulating InP, the first sublayer and the second sublayer forming a pair structure, the second sublayer being located above the multi-quantum well layer, and the second sublayer consisting of one or more layers selected from InGaAs, InAlAs, InGaAlAs, InGaAsP, and InAlAsP.

Buried-type semiconductor optical device

A design supporting apparatus of a semiconductor device, includes sections to perform: setting an impurity concentration with respect to a channel direction and a depth direction to node points arranged discretely in a channel region of a model transistor based on a predetermined concentration distribution rule; calculating an electric characteristic of the model transistor by using the impurity concentration; and storing the impurity concentration as a model parameter of the model transistor in a storage unit, when the calculated electric characteristic and an electric characteristic prepared previously are coincident with each other within a predetermined range. The device characteristic calculating section calculates a surface potential to each of the node points by reducing a dimension of the impurity concentration in the depth direction, corrects the surface potential based on interaction between the node points adjacent to each other, and calculates the electric characteristic by using the corrected surface potential.

Analyzing method of semiconductor device, designing method thereof, and design supporting apparatus

An analysis and design apparatus for semiconductor device, which utilizes a transistor model using accurate channel impurity concentration distribution are provided. The analysis and design apparatus includes a parameter setting portion that divides a channel region into a plurality of regions, and temporarily sets a plurality of impurity concentrations for the plurality of regions as a plurality of parameters. Further, the analysis and design apparatus includes an element characteristic calculation portion that values of electric characteristics of the transistor using surface potential that is calculated by solving a Poisson equation using a plurality of effective impurity concentrations. Moreover, the determination portion compares the calculated values with measured values read from a storage portion based on the structure information, and determines that the plurality of parameters for the transistor when the measured values correspond to the calculated values.

Method and apparatus for analysis and design of a semiconductor device using impurity concentration distribution

In a support apparatus for analysis and design of a semiconductor device, a function indicating an impurity concentration distribution in a channel region of a first transistor in a depth direction is set. A structure data indicating a structure of a transistor device and a measurement value of each of electric characteristics of the transistor are related. A Poisson's equation, which is express by using the function, is solved by using a depletion layer width as a variable to calculate a surface potential, and a first calculation value of the electric characteristic of the first transistor is calculated by using the surface potential. A determining section determines the function to indicate the impurity concentration distribution of a first transistor when a measurement value corresponding to a first structure data which indicates a structure of the first transistor, and the first calculation value are substantially coincident with each other.

Method and apparatus for analyzing and designing semiconductor device using calculated surface potential

From the data of diffusion-length-dependent parameters extracted from the parameters of the transistor model of MOS transistors and from the parameters of transistors having various diffusion lengths, a diffusion-length-dependent parameter correcting unit creates approximate expressions of the diffusion length dependence of these parameters, and calculates parameter correction values to be used instead of original parameter values by using the created approximate expressions. Hence, the correction values can be used easily instead of the original parameter values, whereby a transistor model of MOS transistors having a different diffusion length DL can be created easily. Circuit simulation in consideration of the diffusion length dependence of the drain currents of MOS transistors can thus be carried out, whereby highly accurate simulation can be attained.

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Kanagawa, Japan

Hironori Sakamoto