Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Other

Renesas Electronics Coporation

Hironori Matsushima

Masatoshi Yasunaga

Soshi Kuroda

Kenya Hironaga

Shinji Baba

Shin Nakao

Mitsuyasu Matsuo

Akira Yamazaki

Yoshihiro Tomita

Akihiro Goto

Yoshio Matsuda

Hirofumi Makimoto

Hiroshige Ogawa

To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

Semiconductor device and method of manufacturing the same

To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.

Method of manufacturing semiconductor device

Semiconductor device with copper wire having different width portions

To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100&#xb0; C. to 150&#xb0; C. for dehumidification, a heat treatment (second heat treatment) at 160&#xb0; C. to 230&#xb0; C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Manufacturing method of semiconductor device

Technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of the material constituting a wiring substrate is provided. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100&#xb0; C. to 150&#xb0; C. for dehumidification, a heat treatment (second heat treatment) at 160&#xb0; C. to 230&#xb0; C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

A design support apparatus supports wiring design for bond wires that connect a semiconductor chip and an interposer. The design support apparatus includes a creating unit that creates simulated design data simulating occurrence of fluctuation in an arrangement position of a semiconductor chip on an interposer and occurrence of fluctuation in bond wire connection terminal positions of the interposer, and an analyzing unit that analyzes, based on the simulated design data, deficiencies in manufacturing of semiconductor devices due to the fluctuation in the arrangement position of the semiconductor chip on the interposer and the fluctuation in the bond wire connection terminal positions of the interposer.

Wiring design support apparatus for bond wire of semiconductor devices

There is provided a semiconductor device comprising a semiconductor chip and an electronic part disposed adjacent to each other, wherein a terminal is provided on the side of each of the semiconductor chip and the electronic part, and the terminal is electrically connected to the other terminal in the state where the sides of the semiconductor chip and the electronic part approach to each other. Thereby, the size of the entire semiconductor device can be reduced, and the wiring path can be shortened significantly to improve electrical properties.

Semiconductor device with reduced wiring paths between an array of semiconductor chip parts

A semiconductor chip is attached on a package substrate so as to be electrically connected to it and sealed. A ring member is attached to the package substrate and surrounds the semiconductor chip. A lid member is attached to the ring member and covers the semiconductor chip. The lid member is formed so as to be able to be removed from the ring member without impairing the attachment of the ring member to the package substrate.

Packaged semiconductor device and manufacturing method thereof

A thermosetting epoxy adhesive is applied at the end portion of one surface of the radiating plate onto which a protection ring is bonded, and a protection tape provided with projections is pasted with the thermosetting epoxy adhesive so that projections may project to the opposite side of the radiating plate , to constitute the radiating plate structure as one piece. And the radiating plate structures are stacked within the magazine of the radiating plate mounting machine, each radiating plate structure being picked up by the radiating plate mounting machine, its protection tape being peeled, the radiating plate being mounted at a predetermined position.

Radiating plate structure and method for manufacturing semiconductor devices using the same structure

In the present semiconductor device, signal lines of the first signal layer are led to the lower multi-layer portion via through holes selected under certain conditions so that the crosstalk noise does not become a problem even when the second signal layer is superposed on the first signal layer without providing a plane layer therebetween. In addition, a ground plane is provided in the region of the first signal layer lacking signal lines so that the second signal layer is sandwiched by the planes to form a strip structure even without the provision of a separate plane layer between the first signal layer and the second signal layer. Thus, the number of layers required for the multi-layer substrate can be reduced by eliminating this one unnecessary plane layer.

Semiconductor device

In a semiconductor device, a semiconductor chip is mounted on a planar substrate approximately at the center and a hollow cavity for housing the semiconductor chip is formed by laminating an annular ring member, annular adhesive tapes, and a heat spreader plate on the substrate. A slit is formed in the adhesive tape or the ring member to provide an air vent.

Semiconductor device having a packaged semiconductor element and permanent vent and manufacturing method thereof

Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.

Resin seal semiconductor package and manufacturing method of the same

A semiconductor device includes a multi-layered ball grid array (BGA) substrate with lines and a semiconductor chip having electrodes respectively connected with the lines by soldering bumps wherein the soldering bumps on the periphery of the semiconductor chip are larger in size than soldering bumps in a central portion of the semiconductor chip.

Growing community of inventors

Tokyo, Japan

Hironori Matsushima