Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Zentel Japan Corporation

Renesas Electronics Corporation

Hironori Iga

Takashi Kono

Takashi Kubo

Kenichi Yasuda

Masaru Haraguchi

Yuichi Kunori

Takeshi Hamamoto

Yasuhiko Tsukikawa

Akihiro Hirota

Bunsho Kuramori

Jun Setogawa

Mineo Noguchi

Masahiro Ishihara

Mitsuru Yoneyama

A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.

Semiconductor memory device

A control device of the invention for a semiconductor memory device comprising an interface conforming to JEDEC standard of DDRx-SDRAM or LPDDRx-SDRAM, comprises banks, a read/write control circuit, and a transfer control circuit. Each bank comprises subarrays. Each subarray comprises memory cells arranged along bit lines and word lines. The read/write control circuit controls reading of data from and writing of data to the semiconductor memory device. The transfer control circuit controls data transfer inside the semiconductor memory device and sets to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface.

Semiconductor memory device comprising an interface conforming to JEDEC standard and control device therefor

A semiconductor memory device is provided with a row control circuit, in order to dissolve a Row Hammer issue. The row control circuit is configured to: (A) latches one of (a) a target address upon issuing of an ACTIVE command to the semiconductor memory device, and (b) a row address of a victim cell in which data of a memory cell is affected by the target address, as a victim address by using a predetermined row address latch method; and then, (B) refreshes the victim cell having the victim address by a predetermined refresh method upon issuing of a REFRESH command.

Semiconductor memory device for preventing occurrence of row hammer issue

In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.

Nonvolatile semiconductor memory device having assist gate

A monitor circuit for monitoring external potential EXTVDD and variable delay circuit determine the time interval in which signal ZODACT is being at the L level according to the potential level of external potential EXTVDD, and thus the supplying time of external potential EXTVDD can be dynamically changed. When external potential EXTVDD is at the upper limit of specification of product, the supplying time is short, thereby preventing overcharge of memory cells or bit lines. When external potential EXTVDD is at the lower limit of specification of product, the supplying time becomes longer, thereby ensuring a sufficient over-driving time interval. It is possible to ensure the reliability of the memory cells and perform the reading operation throughout the entire range of the specification of product of external potential EXTVDD. Therefore, it is possible to provide a semiconductor memory device capable of performing a reading operation at high speeds while ensuring the reliability.

Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell

Two input buffer circuits of current mirror type input buffer circuits are combined, and output signals OUT , OUT therefrom are combined to provide output signal OUT via inverter. By inputting complementary clock signals CK, /CK from opposing directions to each other, even complementary clock signals CK, /CK are anti-phase, output signals OUT and OUT are combined in-phase.

Input buffer circuit with constant response speed of output inversion

An input buffer of a signal level conversion circuit according to the present invention includes: a differential amplification circuit of a current mirror amplifier amplifying a potential difference of first and second nodes respectively supplied with an external signal and a reference signal for outputting an internal signal; and a bias circuit applying the same bias potential to the first and second nodes. The bias potential is set in such a way that potentials at the first and second nodes are set to a level where a group of transistors forming the current mirror amplifier can operate in a saturation region regardless of the levels of the external signal and the reference signal.

Signal conversion circuit for stable differential amplification and semiconductor device provided with the same as input buffer

A semiconductor storage device which allows a differential sense amplifier to perform a normal amplifying operation even if a potential difference occurring in a pair of bit lines in readout of memory cell information is small. If a potential difference occurring in the pair of bit lines in readout of memory cell information is small, the differential sense amplifier can not normally perform an operation of amplifying. Adding in the differential amplification circuit DA, the inverting amplification circuit IA is newly provided and the differential amplification circuit DA is caused to operate after a very small potential difference occurring between the bit lines BL and /BL is amplified by the inverting amplification circuit IA.

Semiconductor storage device

A voltage shift circuit included in an input buffer for a semiconductor integrated circuit device converts an external reference potential to a first signal of a predetermined potential. A voltage shift circuit converts the external signal obtained by superposing a logic signal of a small amplitude on an external reference potential to a second signal obtained by superposing a complementary signal of the logic signal with small amplitude on the first signal. Differential amplifying circuit compares the potentials of the first signal and the second signal and applies a signal corresponding to the result of comparison to internal circuitry. Therefore, normal operation is ensured even when an arbitrary potential between 1.25 V to 2.9 V is applied as the external reference potential.

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Tokyo, Japan

Hironori Iga