Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electrical Industrial Co., Ltd.

Matsushta Electric Co., Ltd.

Hironori Akamatsu

Toru Iwata

Yutaka Terada

Takashi Hirata

Hisakazu Kotani

Satoshi Takahashi

Hiroyuki Yamauchi

Masashi Agata

Yoshihide Komatsu

Hirohito Kikukawa

Shunichi Iwanari

Akihiro Sawada

Toshio Yamada

Tadahiro Yoshida

Keiichi Kusumoto

Tsutomu Fujita

Yukio Arima

Katsuji Satomi

Kazuo Itoh

Ichiro Nakao

Marefusa Kurumada

Junko Matsushima

Akira Matsuzawa

Yoshinobu Yamagami

Satoshi Ishikura

Hirokazu Sugimoto

Toshikazu Suzuki

Hirohisa Ohtsuki

Kazuko Nishimura

Junji Hirase

Makoto Kojima

Takefumi Yoshikawa

Akinori Shibayama

Yoshiro Nakata

Susumu Akamatsu

Takashi Hori

Mitsuyasu Ohta

Kazuyoshi Nishi

Toshiaki Tsuji

Koichi Sugimoto

Kazuhiro Matsuyama

Tomohiro Kurozumi

Shoichiro Tada

Tsuoshi Shiragasawa

In a semiconductor memory device, a non-volatile element sectionstores information necessary for rescuing a main memory cell, as storage information, in a non-volatile element. When rescue information Sis newly outputted by a redundancy rescue section, a rescue determination sectiondetermines whether or not a main memory cell is to be rescued, based on storage information Sstored in the non-volatile element section, and the rescue information Swhich is newly outputted. The non-volatile element sectionrenews the storage information based on a determination result from the rescue determination section. Thus, on the assumption that power is turned off each time a voltage condition is changed, the semiconductor memory deviceis capable of determining whether or not the rescue is to be performed, based on results of testings performed under a plurality of voltage conditions.

Semiconductor memory device

A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistorsandincluded in a latch section is different from at least one of a potential supplied to a word lineand a potential supplied to bit linesand; a latch potential control circuitfor switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin; and a read/write control circuitfor controlling the potential supplied to the sources of the load transistorsandto be lower than at least one of the potential supplied to the word lineand the potential supplied to the bit linesand, during an arbitrary period of at least a read operation in the test mode.

The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macrosAandAincludes a memory cell arrayA-connected to word lines WLto WLand bit lines and a redundant circuit that replaces a defective bit line of the memory cell array to a normal bit line and a redundant bit line BLAand outputs defect information to a redundant signal line RA. The redundant memory macroA includes a redundant memory cell array connected to redundant word lines and the redundant bit line, and a first word line connection circuit that connects a word line corresponding to a memory macro to be repaired and disconnects a word line corresponding to a normal memory macro from the redundant word line.

Semiconductor integrated circuit including memory macro

A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistorsandincluded in a latch section is different from at least one of a potential supplied to a word lineand a potential supplied to bit linesanda latch potential control circuitfor switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pinand a read/write control circuitfor controlling the potential supplied to the sources of the load transistorsandto be lower than at least one of the potential supplied to the word lineand the potential supplied to the bit linesandduring an arbitrary period of at least a read operation in the test mode.

The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macros includes a memory cell array connected to word lines and bit lines and a redundant circuit that replaces a defective bit line of the memory cell array to a normal bit line and a redundant bit line and outputs defect information to a redundant signal line. The redundant memory macro includes a redundant memory cell array connected to redundant word lines and the redundant bit line, and a first word line connection circuit that connects a word line corresponding to a memory macro to be repaired and disconnects a word line corresponding to a normal memory macro from the redundant word line.

A static random access memory (SRAM) includes a memory array, a sense amplifier circuit, a replica circuit and a dummy cell. The replica circuit has the same elements as memory cells, and includes plural replica cells which output a signal whose level corresponds to the number of stages provided to a common replica bit line. The dummy cell is connected as a load with the common replica bit line. The source of a drive transistor of the dummy cell is connected with a power source which is at the High level. This suppresses a leak current flowing from a replica bit line to the dummy cell.

Static random access memory (SRAM) with replica cells and a dummy cell

A memory circuitincludes: a feed-through input terminalfor inputting a signal different from a signal to be inputted when reading and writing memory cells; an intermediate buffer circuitprovided between regions where the memory cells are arranged, for relaying the signal inputted through the feed-through input terminal; and a feed-through output terminalfor outputting the signal relayed by the intermediate buffer circuit. Connections between the feed-through input terminaland the intermediate buffer circuitand between the intermediate buffer circuitand the feed-through output terminalare established by feed-through wires, respectively. The feed-through wiresare not connected to either a wire to be used when reading and wiring the memory cells, or the memory cells.

Memory circuit and method of generating the same

A dummy cell includes two series-connected OFF-state transistors, one end of the series circuit which is formed by these two transistors is connected with a constant voltage source, and the other end of the series circuit is connected with a replica bit line. This suppresses a leak current flowing from the replica bit line to the dummy cell and therefore gives optimal start-up timing to a sense amplifier circuit.

Semiconductor memory device and circuit layout of dummy cell

A semiconductor memory device may include: (1) a word line drive circuit, having a drive transistor disposed between a positive power supply and a word line, (2) a circuit for turning the drive transistor OFF after an output of the word line drive circuit reaches a high level, and (3) a word-line-voltage increasing circuit for increasing a voltage of the word line after the drive transistor turns OFF. The word-line-voltage increasing circuit includes a coupling capacitor, one end of which is connected to the word line, and a capacitor drive circuit, an output end of which is connected to the other end of the coupling capacitor. The capacitor drive circuit switches its output from a low level to a high level at a timing when the drive transistor is OFF.

A semiconductor memory device capable of enhancing a production yield is provided. A dummy control circuit activates a first dummy column including a plurality of dummy cells placed at a position close to a row decoder in a row direction and a second dummy column including a plurality of dummy cells placed at a position farthest from the row decoder in a row direction with a plurality of memory cells interposed between the first dummy column and the second dummy column, through first and second dummy word lines. A dummy column selector selects either one of a signal on a first dummy bit line connected to the first dummy column and a signal on a second dummy bit line connected to the second dummy column, and outputs the selected signal to an amplifier control circuit. The amplifier control circuit generates an amplifier startup signal with respect to an amplifier circuit based on a signal from the dummy column selector.

A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly. Consequently, even when the power supply voltage is made lower than the set voltage-detecting level, the first semiconductor integrated circuit properly operates until the power supply voltage reaches a predetermined lower limit of operating voltage. Thus, evaluation of operation is possible under low-voltage conditions.

Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system

A network apparatus is provided, which allows another network apparatus to recognize the disconnection with reliability, if a power supply to the network apparatus is interrupted. A control unit operating with a first power supply outputs a first signal, which is level-converted and supplied as a second signal to an intermediate potential supply unit operating with a second power supply. In the intermediate potential supply unit, a switch receives a reset signal as a switch signal and outputs, when the power supply is interrupted, a ground potential to a driver instead of the second signal. As a result, an intermediate potential supplied to a cable is forcibly set to the ground potential.

Network apparatus

A semiconductor memory device capable of accurately simulating a read-out timing of a memory cell and enhancing a production yield is provided. A dummy column selector is placed so as to be connected to dummy bit lines, and a plurality of dummy cells driving the dummy bit lines are placed at positions farthest in a column direction on a memory array from the side where an amplifier circuit is placed. This configuration allows a timing for driving the bit lines by the memory cells that are placed similarly at positions farthest from the amplifier circuit to be simulated accurately, thus enabling the generation of an amplifier startup signal without delay. Furthermore, a plurality of dummy word lines respectively connected to the plurality of dummy columns allow for readily switching from a dummy cell with a defect to a normal dummy cell.

A memory array portion, a connection circuit serving as an interface of the memory array portion and a signal wiring connecting the memory array portion to the connection circuit are provided. Mesh wirings comprising first and second wiring layers are provided on the memory array portion. The connection circuit is connected to a plurality of signal lines comprising a third wiring layer provided on the memory array portion, the connection circuit or the signal wiring, through an intermediate wiring comprising the second wiring layer. The region where the intermediate wiring is provide on the memory array portion or on the signal wiring, and the mesh wiring comprising the second wiring layer is not present on the region where the intermediate wiring is provided.

Memory macro and semiconductor integrated circuit

First and second nodes are coupled together by a bus. The first node includes a detecting circuit for detecting the maximum data transfer capability of a connected node, at least two receiving circuits for receiving data from the bus, and a controlling circuit for selecting, based on an output signal from the detecting circuit and for optimizing the configuration of a receiving unit so as to bring the other of the receiving circuits to a stop. The second node includes a transmitting circuit for transmitting data to the bus and a notifying circuit for notifying the first node of its own maximum transfer capability.

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Osaka, Japan

Hironori Akamatsu