Hitachi, Ltd.

Nec Corporation

Hironobu Sakata

Hideo Ohata

Kazuya Sato

Naoshi Maniwa

Katsutaka Inoue

Proposed are a method and a device for managing the performance of a storage apparatus which uses a combination of different types of drive devices which mutually have different limits as its storage medium so that measures can be systematically taken against problems that may arise in the future as a result of the drive devices reaching their limit. Based on a premise of being able to tier two or more types of storage mediums which have mutually different rewriting limits and response performances and migrate data between the respective tiers according to the response performance, a performance management device estimates a decrement of a storage capacity pursuant to each of the two or more types of storage mediums reaching a rewriting limit, estimates a performance influence on the virtual volume and a timing of occurrence, and displays information related to the estimated performance influence and the timing of occurrence.

Method and device for managing performance of storage apparatus

Multiple storage apparatuses each provide a virtual logical volume composed of multiple logical pages to a host computer. A management computer determines a target logical page to which data are migrated to achieve a volume goal performance on the basis of access path information that can identify a storage apparatus that receives an I/O request in which the virtual logical volume is specified, an actual volume response performance, the volume goal performance to be attained, a page response performance of the logical page, and storage destination information that can identify a storage apparatus in which a storage area allocated to the logical page is present, and migrates data of the logical page between storage apparatuses.

Method for selecting a page for migration based on access path information and response performance information

A multi-processing device includes three or more processing systems, each having a processor and a corresponding main memory connected to each other by means of an individual memory bus. The multi-processing device also includes a common memory bus connectable to all the processors and all the main memories of the respective systems, an asynchronism detection circuit connected to the respective processors to produce an asynchronism detection signal indicating which system or systems are in asynchronous state, and a device control circuit responsive to the asynchronism detection signal to send a common memory bus select signal to the main memory of each failed system to change its bus connection from the individual memory bus to the common memory bus. The device control circuit also generates a master designation signal for allowing an arbitrary processor of the normal non-faulty systems to be designated as a master processor, and a copy request signal to the respective processors. The copy request signal causes the master processor to copy the content of the main memory of the normal system to the main memory of each failed system. When the synchronization between the respective systems is established, the device control circuit outputs a restart request signal to the respective processors, thus initiating the execution from a fixed, stored address in a control memory of each processor to enable synchronous starting of all of the processor. The multi-processing device further includes a communication control circuit connected to the common memory bus, thus permitting parallel loading of an initial program to the main memories of the respective systems for achieving recovery in the case where all the systems are asynchronous with each other.

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Tokyo, Japan

Hironobu Sakata