Renesas Electronics Corporation

Nec Corporation

Kabushiki Kaisha Toshiba

Nec C Orporation

Hironobu Miyamoto

Tatsuo Nakayama

Yasuhiro Okamoto

Yuji Ando

Takashi Inoue

Kazuki Ota

Masaaki Kuzuhara

Yoshinao Miura

Kensuke Kasahara

Hiroshi Kawaguchi

Akio Wakejima

Toshiyuki Takewaki

Yoko Masuo

Yuji Takahashi

Yasuhiro Murase

Yasuo Ohno

Naotaka Kuroda

Nobuyuki Hayama

Kazuaki Kunihiro

Kohji Matsunaga

Katsumi Yamanoguchi

Takayuki Nagai

Kouji Matsunaga

Shinichi Miyake

Kazuomi Endo

Ryohei Nega

Taichiro Yamanaka

Ichiro Masumoto

Nobuhiro Nagura

Masaaki Kanazawa

Hajime Yamazaki

Koichi Arai

Masahiro Tanomura

Naotaka Iwata

Shinji Yonezawa

Hidenori Shimawaki

Kenichi Hisada

Wataru Okamoto

Koji Hataya

Atsushi Tsuboi

Tatsuya Usami

Hirokuni Yano

Kazuhiko Onda

Tohru Kawai

Yoichi Makino

Takehiko Kato

Masami Sawada

Koji Matsunaga

Yoshimasa Aoyama

Kazuaki Ashizuka

Tatsuo Nakayawa

First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

Manufacturing method of semiconductor device and semiconductor device

A Semiconductor device includes a substrate and a thermal conductive film. The substrate has a top surface and a back surface which oppose with each other. A first opening is formed on the back surface of substrate. The thermal conductive film includes a first thermal conductive portion formed in the first opening. The first thermal conductive portion is embedded in the first opening such that a void is formed in the first opening.

Semiconductor device

Characteristics of a semiconductor device using a nitride semiconductor are improved. A semiconductor device of the present invention includes a buffer layer, a channel layer, a barrier layer, a mesa-type 2DEG dissolving layer, a source electrode, a drain electrode, a gate insulating film formed on the mesa-type 2DEG dissolving layer, and an overlying gate electrode. The gate insulating film of the semiconductor device includes a sputtered film formed on the mesa-type 2DEG dissolving layer and a CVD film formed on the sputtered film. The sputtered film is formed in a non-oxidizing atmosphere by a sputtering process using a target including an insulator. This makes it possible to reduce positive charge amount at a MOS interface and in gate insulating film and increase a threshold voltage, and thus improve normally-off characteristics.

Method of manufacturing semiconductor device and the semiconductor device

A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.

Semiconductor device and manufacturing method thereof

Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.

Semiconductor device and method of manufacturing the semiconductor device

A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (&#x3b8;1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed.

Semiconductor device and method for manufacturing the same

Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes a buffer layer composed of a first nitride semiconductor layer, a channel layer composed of a second nitride semiconductor layer, and a barrier layer composed of a third nitride semiconductor layer, which are sequentially laminated, and a cap layer composed of a fourth nitride semiconductor layer of mesa type, which is formed over the barrier layer. The semiconductor device also includes a source electrode formed on one side of the cap layer, a drain electrode formed on the other side of the cap layer, and a first gate electrode formed over the cap layer. The first gate electrode and the cap layer are Schottky-joined. A Schottky gate electrode (the first gate electrode) is provided over the cap layer in this way, so that when a gate voltage is applied, an electric field is applied to the entire cap layer and a depletion layer spreads. Therefore, it is possible to suppress a gate leakage current.

Semiconductor device and manufacturing method of semiconductor device

A mesa portion of a semiconductor device, which includes a channel base layer formed of a first nitride semiconductor layer, a channel layer formed of a second nitride semiconductor layer, a barrier layer formed of a third nitride semiconductor layer, a mesa-type fourth nitride semiconductor layer, a gate insulating film that covers the mesa portion, and a gate electrode formed over the gate insulating film, is used as a co-doped layer. The mesa portion is used as the co-doped layer, so that interface charges generated at an interface between the gate insulating film and the mesa portion can be cancelled by p-type impurity or n-type impurity in the co-doped layer and a threshold potential can be improved. Further, the fourth nitride semiconductor layer is n-type until the gate insulating film is formed, and the fourth nitride semiconductor layer is made neutral or p-type after the gate insulating film is formed.

A semiconductor device includes a channel layer formed over a substrate, a barrier layer formed on the channel layer and a gate electrode. A second gate electrode section is formed on the gate electrode via a gate insulating film. It becomes possible to make an apparent threshold voltage applied to the second gate electrode of a MISFET higher than an original threshold voltage applied to the gate electrode for forming a channel under the gate electrode by providing an MIM section configured by the gate electrode, the gate insulating film and the second gate electrode in this way.

A MISFET is formed to include: a co-doped layer that is formed over a substrate and has an n-type semiconductor region and a p-type semiconductor region; and a gate electrode formed over the co-doped layer via a gate insulation film. The co-doped layer contains a larger amount of Mg, a p-type impurity, than that of Si, an n-type impurity. Accordingly, the carriers (electrons) resulting from the n-type impurities (herein, Si) in the co-doped layer are canceled by the carriers (holes) resulting from p-type impurities (herein, Mg), thereby allowing the co-doped layer to serve as the p-type semiconductor region. Mg can be inactivated by introducing hydrogen into, of the co-doped layer, a region where the n-type semiconductor region is to be formed, thereby allowing the region to serve as the n-type semiconductor region. By thus introducing hydrogen into the co-doped layer, the p-type semiconductor region and the n-type semiconductor region can be formed in the same layer.

The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

Semiconductor device and a method for manufacturing a semiconductor device

A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.

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Tokyo, Japan

Hironobu Miyamoto