Hitachi, Ltd.

Renesas Technology Corp.

Hironobu Hasegawa

Shiro Baba

Yasushi Akao

Toru Baji

Atsushi Kiuchi

Koki Noguchi

Hiroshi Ohsuga

Hiroyuki Sasaki

Masahiko Uraguchi

Kunihiko Nishiyama

Tadashi Teranuma

Yoshihiko Tsuchihashi

A built-in memory is divided into the following two types: first memoriesandand second memoriesand, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU corecan simultaneously transfer two data values from the built-in memory to a DSP engine. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU corecan access an external memory in parallel with the access to the second memoriesandand the first memoriesand

Microcomputer

A data processor has a first bus master module, first bus slave module and first bus right arbitrating circuit connected to a first bus, a second bus master module, second bus slave module and second bus right arbitrating circuit connected to a second bus, and a bus bridge circuit connecting the first and second buses. The bus bridge circuit has a first transfer controller, responsive to an access request from the first bus to the second bus, for obtaining a bus right of the second bus, and a second transfer controller, responsive to an access request from the second bus to the first bus, for obtaining a bus right of the first bus. The second bus has a first path connecting the second bus slave module and the first transfer controller and a second path connecting the second bus master module and the second transfer controller.

Data processor

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and

Microprocessor having a DSP and a CPU and a decoder discriminating between DSP-type instructions and CUP-type instructions

A built-in memory is divided into the following two types: first memories and and second memories and , and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core can simultaneously transfer two data values from the built-in memory to a DSP engine . Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core can access an external memory in parallel with the access to the second memories and and the first memories and

A data processor has a ROM that holds a boot program for causing the CPU to transfer a debug program from a serial interface circuit to a debug-use RAM area. When supplied externally with an SDI boot command, the serial interface circuit outputs an SDI interrupt request signal (SDI_boot) to an interrupt controller. The signal causes the CPU to execute the boot program. Debug operations are varied as per the contents of the downloaded debug program, and data exchanges upon debugging are carried out serially.

Data processor and data processing system

A data processor has a ROM that holds a boot program for causing the CPU to transfer a debug program from a serial interface circuit to a debug-use RAM area. When supplied externally with an SDI boot command, the serial interface circuit outputs an SDI interrupt request signal (SDI.sub.-- boot) to an interrupt controller. The signal causes the CPU to execute the boot program. Debug operations are varied as per the contents of the downloaded debug program, and data exchanges upon debugging are carried out serially.

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Growing community of inventors

Kodaira, Japan

Hironobu Hasegawa