Kabushiki Kaisha Toshiba

Sony Semiconductor Solutions Corporation

Hironobu Fukui

Kazuya Ohuchi

Mariko Takayanagi

Shuhei Maeda

Hirofumi Yamashita

Takashi Tanaka

A solid-state imaging element according to an aspect of the present disclosure includes a first semiconductor substrate (), an insulating layer () and a second semiconductor substrate (), a floating diffusion layer (FD) of the first semiconductor substrate (), a transfer gate (TG) of the first semiconductor substrate (), a first through wire () electrically connected to the floating diffusion layer (FD) and penetrating the insulating layer () and the second semiconductor substrate (), a second through wire () electrically connected to the transfer gate (TG) and penetrating the insulating layer () and the second semiconductor substrate (), a wiring layer () stacked on the second semiconductor substrate () and having a wiring electrically connected to the first through wire () or the second through wire (), and an adjustment layer that is provided on the second semiconductor substrate () so as to be in contact with both or one of the first through wire () and the second through wire () and adjusts a capacitance between the transfer gate (TG) and the floating diffusion layer (FD).

Solid-state imaging element and electronic device

A solid-state imaging device including: a semiconductor substrate having a first surface and a second surface opposed to each other, and including a photoelectric converter provided for each of pixel regions; an impurity diffusion region provided, for each of the pixel regions, in proximity to the first surface of the semiconductor substrate; and a contact electrode embedded in the semiconductor substrate from the first surface, and provided over and in contact with the impurity diffusion regions each provided for each of the pixel regions adjacent to each other.

Solid-state imaging device and solid-state imaging apparatus

A solid-state imaging device includes a first semiconductor substrate, an isolation region, a charge holding section, and a charge accumulation section. The first semiconductor substrate is a substrate in which a photoelectric converter is provided for each of unit regions. The isolation region is provided to run through the first semiconductor substrate in a thickness direction and electrically isolates the unit regions from each other. The charge holding section is electrically coupled to the photoelectric converter and configured to receive signal charge from the photoelectric converter. The charge accumulation section is shared by two or more of the unit regions and is a section to which the signal charge is transferred from the photoelectric converter and the charge holding section of each of the unit regions sharing the charge accumulation section.

Solid-state imaging device

There is provided a solid-state imaging device that includes a photoelectric conversion unit, a transfer gate, a floating diffusion unit, and a transistor. The photoelectric conversion unit produces a charge according to incident light. The transfer gate has a columnar shape having an opening that is continuous in a vertical direction, and transfers the charge from the photoelectric conversion unit. The floating diffusion unit is formed extending to a region surrounded by the opening of the transfer gate, and converts the transferred charge into a voltage signal. The transistor is electrically connected to the floating diffusion unit via a diffusion layer.

Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus

A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.

Metal oxide semiconductor (MOS) device comprising a buried region under drain

A semiconductor device including silicide layers with different thicknesses corresponding to diffusion layer junction depths, and a method of fabricating the same are provided. According to one aspect, there is provided a semiconductor device comprising a first semiconductor element device and a second semiconductor element device, wherein the first semiconductor element device includes a first gate electrode, first diffusion layers disposed to sandwich the first gate electrode, and having a first junction depth, and a first silicide layer disposed in the first diffusion layers and having a first thickness, and the second semiconductor element device includes a second gate electrode, second diffusion layers disposed to sandwich the second gate electrode, and having a second junction depth greater than the first junction depth, and a second silicide layer disposed in the second diffusion layers and having a second thickness greater than the first thickness.

Semiconductor device and method of fabricating the same

Metal oxide semiconductor (MOS) type semiconductor device and having improved stability against soft errors

A data holding circuit includes a first data holding unit, a second data holding unit and a selection unit. In the first data holding unit, a probability of a soft error at a time when input data has a first level is lower than a probability of a soft error at a time when the input data has a second level. In the second data holding unit, a probability of a soft error at a time when the input data has the second level is lower than a probability of a soft error at a time when the input data has the first level. The selection unit selects an output from the first data holding unit when the input data has the first level, and selects an output from the second data holding unit when the input data has the second level.

Data holding circuit

An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.

Semiconductor device and method of manufacturing the same

A semiconductor device has a semiconductor substrate, a first transistor having a first gate electrode formed of a polycrystalline silicon germanium film as formed above said semiconductor substrate, and a second transistor having a second gate electrode which is formed of a polycrystalline silicon germanium film as formed above the semiconductor substrate and which is different in concentration of germanium from the first gate electrode.

A semiconductor device according to one aspect of the present invention, is a semiconductor device comprising: a first MOS field effect transistor of an n-type including a first oxynitride film as a first gate insulator film; and a second MOS field effect transistor of a p-type including a second oxynitride film as a second gate insulator film, the second MOS field effect transistor being disposed adjacent to the first MOS field effect transistor; wherein a concentration of nitrogen in the first gate insulator film is different form that in the second gate insulator film.

Growing community of inventors

Kawasaki, Japan

Hironobu Fukui