International Business Machines Corporation

Hironari Nishino

Johji Mamiya

Hirokazu Nishimura

Masayuki Sohda

Kohnji Ishii

A synchronous signal separation circuit is disclosed which separates and fetches a synchronous signal from a video signal to which the synchronous signal has been added. The synchronous signal separation circuit includes an amplifier for amplifying a voltage of the video signal to output an amplified signal having an amplified voltage which is within a predetermined dynamic range. A voltage generator outputs a variable offset voltage to the amplifier for shifting a reference level of the amplified voltage to a predetermined level. A synchronous signal fetch means which, by comparing the amplified video signal with a threshold voltage in which the variable offset voltage has been adjusted based on the degree of amplification of the amplifier, fetches only the synchronous signal from the video signal.

Synchronous signal separation circuit

To generate a dot clock for a liquid crystal display device from a horizontal sync signal with reduced skew, a phase locked loop (PLL) is divided into three functional parts. The first part generates a particular frequency by supplying voltage from a latch type DAC (digital/analog converter) to a VCO (voltage controller oscillator). A horizontal sync signal is estimated from the dot clock signal that is finally generated and the output value of the DAC is increased or decreased in accordance with the difference between this estimated horizontal sync signal and the actual horizontal sync signal. This increase or decrease correction is made at, for example, the vertical sync timing. The second part achieves synchronization. A signal corresponding to the phase error between the actual horizontal sync signal and the dot clock signal is added to the signal from the DAC to control the phase of the dot clock. The third part is a PLL for generating the dot clock in accordance with the signal generated by the first part at the particular frequency.

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Fujisawa, Japan

Hironari Nishino