Hitachi, Ltd.

Hiromitsu Yamada

Katsuyoshi Suzuki

Naoki Kato

Masato Mogaki

Katsuaki Hongyo

Yoshiaki Miyazaki

In a computer-aided design (CAD) method for the intra-chip wiring in a hierarchical implementation design of a semiconductor integrated circuit, wiring pattern spaces from block edge terminals are guaranteed while preventing any wiring detour in inter-block nets. Logical line connecting information and implementation information such as contours of parts and terminal positions are inputted from a logical file and a library to extract block edge terminals so as to define a block boundary in accordance with layout positions of parts to be allocated. On the block boundary defined, one virtual terminal is generated for each block edge terminal to dispose wirings between the block edge terminals and the associated virtual terminals. An intra-block net wiring is then achieved without a short circuit to the wirings between the block edge terminals and the associated virtual terminals. Finally, the virtual terminals and the wiring pattern between the block edge terminals and the associated virtual terminals are deleted.

Hierarchical wiring method for a semiconductor integrated circuit

In designing wiring for semiconductor integrated circuits, wiring channels are assigned to reduce a signal delay time developed parallel traces. The selection of the wiring channels for all of the wiring oriented nets of the circuits is based on the trunk trace length between the terminals. For the longer trunk trace lengths, a double-pitch wiring channel is assigned. First, the determined trunk-trace lengths are sorted in decreasing order of length. Then, a double-pitch wiring channel is assigned for the trunk-trace lengths that are greater than a predetermined length. When no double pitch channels remain, single pitch channels are used.

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Hadano, Japan

Hiromitsu Yamada