Matsushita Electronics Corporation

Matsushita Electric Industrial Co., Ltd.

Hiromitsu Takagi

Gota Kano

Iwao Teramoto

Daisuke Ueda

Akio Shimano

Shotaro Umebachi

An insulated gate FET such as a power MOS FET is made by forming a rectangular parallelepiped-shaped recess in a direction that the side walls of the recess make 45.degree. angle against the &lt;100&gt; direction of the silicon substrate having (100) plane as principal surface, and the vertical side walls of (010) or (001) planes are used as channel region of the insulated gate FET, thereby assuring a large electron mobility in the channel, hence low channel resistance suitable for high power operation.

Vertical insulated gate FET

A novel self-align type method of making an FET with a very short gate length and a good high frequency characteristic, and a low noise characteristic, the method comprising the steps of:

Method of making FET utilizing shadow masking and diffusion from a doped

An epitaxial layer having a specified conductivity type formed on a semiinsulative or high resistivity semiconductor substrate or insulative substrate is anodized (anodically oxidized) by a predetermined D.C. current under an illumination of light of a predetermined intensity, thereby a depletion layer is formed beneath an oxide layer, which is formed by the anodizing, and the anodizing ceases in areas where the bottom face of the depletion layer reaches the semiinsulative or high resistivity semiconductor substrate or insulative substrate thus retaining a layer of highly uniform thickness layer of the epitaxial grown layer on the substrate.

Method of making semiconductor device

In the process of forming a thermal oxide film or heat treatment of an oxide film in making a semiconductor device comprising a compound semiconductor of arsenic, the semiconductor is handled in an atmosphere containing arsenic oxide vapor in order to prevent evaporation of the arsenic tri-oxide in the thermal oxidation film or the oxide film under heat treatment, thereby to form a thermal oxide film having good chemical stability and good electrical characteristics, or to improve the oxide film so as to have good chemical stability and good electrical characteristics.

Selective thermal oxidation of As-containing compound semiconductor

Both source-electrodes (S1 and S2) or both drain-electrodes of a pair of field-effect transistors (FETs) (F1 and F2) of n-channel type and p-channel type, respectively, both to be electrically actuated in a depletion mode are connected to each other, or the source of one FET and the drain of the other FET are connected to each other, through a variable resistance element (F3) inbetween, whereby the pair of FETs (F1 and F3) are series-connected through the variable resistance element (F3) inbetween, the gate-electrode (g1 or g2) of each FET is connected to the drain-electrode (d2 or d1) or the source-electrode of the other FET (F2 or F1) that is not connected to the variable resistance element (F3), and a pair of external terminals (1 and 2) are connected to said gate electrodes (g1, g2) those are connected to said drain electrodes (d2 and d1) or source electrodes. When a voltage of specified range is applied across both non-series-connected electrodes, i.e., the two external terminals, the resulting voltage-current characteristic presents a so-called dynatron-type characteristic, producing a negative-resistance phenomenon, and a curve of voltage-current characteristic changes responding to the value of control signal to the variable resistance element. Since this device is a negative resistance of variable characteristic this device can be utilized for switching, signal relaying, memorization and other various controlling or data processing uses.

Growing community of inventors

Shiga, Japan

Hiromitsu Takagi