Micron Technology Incorporated

Hiromitsu Oshima

Che-Chi Lee

Tsuyoshi Tomoyama

Toshiyasu Fujimoto

Tomohiro Iwaki

An apparatus includes: a semiconductor substrate; an isolation region in the semiconductor substrate, the isolation region including an isolation trench filled with an insulating material therein; a plurality of island-shaped active regions in the semiconductor substrate surrounded by the isolation region; and a buried word-line having a bottom, the buried word-line at least passing across the isolation region between the plurality of active regions; wherein the isolation trench includes upper, middle and lower portions, each of the upper and lower portions has a substantially flat surface and the middle portion has a bulged surface.

Semiconductor memory device and method of forming the same

Some embodiments include a method of patterning a target material. An assembly is provided which has a masking material over the target material. First lines are formed over the assembly. The first lines extend along a first direction and are laterally spaced from one another by first spaces. Second lines are formed over the first lines. The second lines extend along a second direction which crosses the first direction, and are laterally spaced from one another by second spaces. The second lines cross the first lines at first crossing regions. The second spaces cross the first spaces at second crossing regions. A pattern includes the first and second crossing regions. The pattern is transferred into the masking material to form holes in the masking material in locations directly under the first and second crossing regions. The holes are extended into the target material.

Patterning methods

Apparatus and methods of forming an apparatus can include one or more cell contacts in an integrated circuit in a variety of applications. In various embodiments, a resist underlayer can be formed on a dielectric spacer formed on a structure for a cell contact, where the structure can include a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region disposed on a dielectric region. The resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region can be processed to form an array of columns in the dielectric region. Regions between the columns of the array of columns can be filled with conductive material, forming the cell contact. Additional apparatus, systems, and methods are disclosed.

Growing community of inventors

Higashihiroshima, Japan

Hiromitsu Oshima