Hitachi, Ltd.

Hiromitsu Mishimagi

Hisashi Nakamura

Kanji Otsuka

Masao Kawamura

Toshiyuki Sakuta

Kazuya Ito

Makoto Homma

Shigeo Kuroda

Kunizo Sahara

Masanori Tazunoki

Hinoko Kurosawa

Toshihiko Satoh

Minoru Enomoto

Keiji Sasaki

To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.

Wafer scale or full wafer memory system, packaging method thereof, and

Wafer scale of full wafer memory system, packaging method thereof, and

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Akishima, Japan

Hiromitsu Mishimagi